Product category:
Intellectual Property Cores
News Release from: MIPS Technologies
Edited by the Electronicstalk Editorial
Team on 04 November 2005
Sarnoff extends functionality of MIPS
products
Sarnoff is to offer its latest H.264 codecs on the industry-standard MIPS architecture, allowing MIPS Technologies to offer its customers a broad range of video solutions for the first time.
MIPS Technologies and Sarnoff have announced that Sarnoff will offer its latest H.264 codecs on the industry-standard MIPS architecture, allowing MIPS Technologies to offer its customers a broad range of video solutions for the first time This offering enables mobile TVs, cellphones, VoIP terminals, and other portable media devices using the MIPS architecture to encode, decode, and display vivid, high-resolution, full-motion video for television, teleconferences, movies, camcorder features, music videos and other business and entertainment applications
This article was originally published on Electronicstalk on 23 Feb 2001 at 8.00am (UK)
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The codecs, part of Sarnoff's line of SelectCores silicon IP, can accommodate video at up to 30 frames/second and up to VGA resolution (640 x 480).
They are compatible with the ITU H.264 and MPEG-4/AVC standards, and offer superior image quality derived from Sarnoff's Emmy Award-winning video technology.
Included hardware-based accelerators may be implemented for maximum flexibility.
Further reading
64bit soft core has integral floating-point unit
In response to customer demand for a 64bit synthesisable processor core with floating point, MIPS Technologies has introduced the MIPS64 5Kf core.
Boosted performance for 32bit soft core
MIPS Technologies has launched its next generation 32bit, high-performance, low-power core, the MIPS32 4KE family.
Software-only codecs are also available, optimised for the MIPS instruction set.
"This is good news for current and future users of the MIPS architecture", said Will Strauss, President of Forward Concepts, a market research firm based in Tempe, Arizona, USA.
"Adding just enough silicon to speed up a software-based system retains all the advantages of programmability, yet achieves the throughput required".
"MIPS-Based cores are widely used as host CPUs, and adding video solutions complements their audio offerings".
"The MIPS architecture is the de facto standard in many digital consumer applications that would benefit from intensive video decoding, and we're delighted to support these cores with our codecs", said Bill Mayweather, Senior Director, IC Systems and Services at Sarnoff.
"Chip designers now have ready access to a highly efficient implementation of H.264 technology that combines design flexibility and the highest quality video with the lowest power consumption".
According to Pat Hays, Vice President of Engineering at MIPS Technologies, the addition of Sarnoff's codecs extends the functionality of MIPS-based products.
"The digital consumer electronics industry is experiencing dynamic change driven by increased demand for more intuitive services and media-rich content", he said.
"Bringing H.264 video to the MIPS architecture enables our customers to meet this demand".
Sarnoff's H.264 silicon IP draws low power for long battery life.
By choosing which of the hardware-based accelerators are implemented, users can optimise the cost/power tradeoffs to the specific device being designed.
This allows them to customise device performance and maintain brand differentiation.
The IP also allows software or hardware to be used interchangeably for given functions.
Device makers can freely integrate proprietary technology with the IP to enable specific functions or boost performance.
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