Product category:
Intellectual Property Cores
News Release from: MIPS Technologies | Subject: New Core-Optimised IP Kits
Edited by the Electronicstalk Editorial
Team on 26 July 2006
New core-optimised IP kits
Virage Logic and MIPS Technologies introduce new core-optimised IP kits for MIPS32 24K, 24KE and 34K core families in 90nm G process
MIPS Technologies and Virage Logic, a pioneer in Silicon Aware IP and leading provider of semiconductor intellectual property (IP) platforms, have announced the availability of new jointly-developed Core-optimised IP Kits exploiting Virage Logic's Area, Speed and Power (ASAP) Memory and ASAP Logic High-Speed (HS) IP, the new series of Core-optimised IP Kits provides MIPS Technologies' customers with IP that is specifically tuned to maximise the performance of MIPS processor cores
This article was originally published on Electronicstalk on 23 Feb 2001 at 8.00am (UK)
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The Core-Optimised IP Kits target the MIPS32 24K, 24KE and 34K families of processor cores for manufacture on TSMC's 90nm G process.
The 24K and 24KE processor core families can achieve clock frequencies of 660 MHz, using only nominal threshold transistors when implemented with the Core-optimised IP Kits.
"With the introduction of new Core-Optimised IP Kits for the 90nm G process, our customers can further benefit from our continued relationship with Virage Logic and the combined expertise of two industry leaders," said Jack Browne, vice president of marketing at MIPS Technologies.
"SoC designers can now utilise this added performance more efficiently to accelerate their time-to-market and generate a significant competitive advantage".
"Virage Logic has long been a trusted IP partner that customers turn to for highly differentiated IP that is optimised for performance and reliability," said Jim Ensell, senior vice president of marketing and business development at Virage Logic.
"We're delighted that our collaborative efforts with MIPS Technologies continue to provide our mutual customers with integrated solutions that help them meet their high performance system design requirements".
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