Product category:
Embedded Software and Operating Systems
News Release from: Mistral Solutions | Subject: IPC 2.0
Edited by the Electronicstalk Editorial
Team on 26 January 2007
Library aids multiprocessor design
Mistral Solutions has announced the availability of the latest version of the popular Inter-Processor Communications (IPC) software library - the IPC 2.0 from Curtiss Wright Embedded Computing.
Mistral Solutions has announced the availability of the latest version of the popular Inter-Processor Communications (IPC) software library - the IPC 2.0 from Curtiss Wright Embedded Computing The IPC 2.0 is used for building high-performance multiprocessor DSP VPX and VPX/REDI-based (VITA 46/VITA 48) platforms employing switched interconnect technology
This article was originally published on Electronicstalk on 20 Jun 2008 at 8.00am (UK)
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Designed for use in demanding signal processing applications such as radar, sonar and signal intelligence, the new IPC 2.0, with its support for Serial RapidIO (SRIO) is ideal for DSP applications designed with the latest high bandwidth, switched serial fabric-based VPX technology.
IPC 2.0 supports two communications models.
Its messaging API provides the foundation for control and synchronisation between processors with priority-based, flow-controlled and acknowledged messages.
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IPC 2.0 also provides a global shared memory model that is used for the transfer of large datasets.
With support for global shared memory, IPC 2.0 eases the porting of software between hardware and middleware environments, making it faster and simpler to migrate from legacy VME64x-based platforms to the new high performance VPX/VPX-REDI architectures.
IPC 2.0 VPX/VPX-REDI Hardware Support includes CHAMP-AV6 Quad PowerPC 8641/8641D DSP engine and SVME/DMV-185 PowerPC 8641/8641D SBC.
The IPC library also provides support for high availability systems.
With functionality to allow dynamic entry and exit of nodes from a system, developers can construct systems with n+1 redundant sparing techniques that exhibit minimal downtime to reconfigure after a board failure.
IPC 2.0 provides prioritised, queue-driven flow-controlled message passing for command and control as well as block transfers for high-volume time-perishable data.
A Posix compliant interface is provided with standard open, close, read, write, and ioctl functions.
An extended interface provides control over additional features.
Further, the IPC 2.0 also provides a single API for task-to-task communications where tasks can be resident on the same processor, same board, or on boards connected via switched interconnect.
Data transport features in IPC 2.0 address common scenarios in signal processing algorithms where frequently, a single data matrix is divided between processors and reconstructed during the processing stages.
For corner turn operations, IPC supports multiple senders writing to a single receiver and strided data movements to facilitate operation on large matrices that have been partitioned.
When supported by the operating system, IPC 2.0 can perform copyless message retrieval to eliminate the time wasted by making local copies of incoming messages.
IPC 2.0 is supported for use with the VxWorks 6.3 real-time operating system.
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