Product category:
Embedded Computing and Control
News Release from: MEN Mikro Elektronik | Subject: P699 XMC and P598 ccPMC.
Edited by the Electronicstalk Editorial
Team on 11 January 2008
Universal submodule cuts design times
MEN Micro's USM concept uses one or more IP cores in an FPGA to help designers easily and quickly turn individual I/O requirements into production-ready products
MEN Micro is now offering its FPGA-based Universal Submodule (USMT) concept on two additional mezzanine cards; the P699 XMC and the P598 conduction-cooled PMC (ccPMC) All products based on MEN Micro's USM concept use one or more IP cores in an FPGA to help designers easily and quickly turn individual I/O requirements into production-ready products, reducing design time and costs
This article was originally published on Electronicstalk on 21 May 2002 at 8.00am (UK)
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PXI Systems feature flexible I/O configuration
MEN Mikro Elektronik is launching a complete new range of PXI systems incorporating highly reliable system controllers, I/O boards and mezzanines.
Modules embed industrial I/O
Two new M-Modules are suitable for a wide range of applications requiring digital I/O or analogue switching.
The use of Cyclone FPGAs on the two new cards enables exceptional I/O combinations in a very small space for moderate volumes and at a low cost.
The P699 XMC uses a Cyclone III FPGA with 24,624 LE (logic elements) and the P598 ccPMC features a Cyclone II with 33,216 LE.
Different IP cores allow users to change the functionality of either card without any hardware modifications to the main module.
The corresponding line drivers are implemented on the individually designed USM submodule that plugs into the main XMC or ccPMC.
Because they function independently of other electronic components, the IP cores provide trouble-free, long-term operation over a temperature range of -40C to +85C.
A Nios soft core processor, which features 32Mbyte of DDR2 SDRAM main memory and 2Mbyte (P598) or 4Mbyte (P699) Flash memory, is implemented on the FPGA providing local intelligence to the main module.
A USM development package includes a main PMC with a USM submodule, test hardware and an FPGA package with a Nios CPU, memory control, connection to the PMC, Avalon/Wishbone bridges and detailed documentation.
The Wishbone Bus Maker tool from MEN is included for development of IP cores on the standard Wishbone bus.
The Nios core and the development of IP cores on the Avalon bus require Altera 's Quartus II design environment including the SOPC builder.
MEN Micro also offers design and implementation of IP cores, design of the USM submodules as well as production of main modules and submodules.
In addition to the two new cards, the USM Universal Submodule I/O family also consists of the P599 PMC and the M199 M-Module.
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