Memory controller and PLL IP move down to 65nm

Mosaid has released the industry's first complete DDR SDRAM controller and interface IP, as well as fractional PLL IP, in leading 65nm process technology.

Mosaid Technologies has announced general availability of the industry's first complete DDR SDRAM controller and interface IP, as well as fractional PLL IP, in leading 65nm process technology.

Mosaid Memorise, a complete high-performance DDR SDRAM controller and interface IP solution, and Mosaid Maestro, a highly flexible fractional-N PLL product line, are available now in 65nm process geometry from a leading foundry, and for porting to other foundries.

The SoC industry is rapidly adopting the 65nm process node for the next generation of electronic devices to provide increased functional integration, smaller end-product form factors and lower overall power consumption.

The move to 65nm technology is creating increased demand for superior quality, well-tested semiconductor IP solutions that reduce design time and product risk in small geometries.

"SoC vendors designing for consumer electronics products - particularly portable devices - require IP in 65nm processes that free up chip overhead for increased functionality", said Michael Kaskowitz, Senior Vice President, Semiconductor IP, Mosaid.

"Mosaid's memory controller and PLL solutions in 65nm resolve real-world design problems of performance, power and risk".

Mosaid Memorise offers the highest performance DDR SDRAM memory controller IP available on the market.

Supporting DDR2 datarates up to 1066Mbit/s, Memorise delivers DDR3 performance today.

Mosaid's Maestro fractional-N PLL is a fully integrated programmable low-power high-performance delta-sigma fractional-N PLL.

It is optimised for line operated and battery powered applications where the system clock can operate at datarates as high as 3.2GHz.

The large fractional multiplication range enables the PLL to address many markets and applications with a single, low-cost crystal frequency.

Back to top