PLL chips move to 65nm CMOS process

PLL chips are now available from a leading foundry using a 65nm CMOS process.

Mosaid Technologies has announced working silicon for its PLLs (phase-locked loops) at the 65nm CMOS process node.

Mosaid's PLLs are fabricated in both standard logic and low-power 65nm process nodes at a leading foundry.

System on chip (SoC) designs at 65nm include many IP cores which often have different frequency requirements.

Implementations are simplified using one or more of Mosaid's configurable, high-performance PLLs.

With PLL IP that is already proven at 65nm, designers reduce the risk and development cost for chips that use this IP and the end products in which they are embedded.

"Many SoC designs, including consumer product SoCs, are quickly moving to the 65nm process node to reduce cost and increase functionality", says Michael Kaskowitz, Senior Vice President, Semiconductor IP, Mosaid.

"Our 65nm silicon-proven PLL IP gives our customers time to market and flexibility advantages over the competition".

Mosaid's fractional-N PLL is a fully integrated, programmable, low-power, high-performance delta-sigma, fractional-N product.

It is optimised for line-operated and battery powered applications at system clock rates as high as 3.2GHz.

The large fractional multiplication range of Mosaid's PLL enables it to address many markets and applications with a single, low-cost crystal frequency, thus reducing inventory, delivery time and bill of materials (BOM) cost.

Applications for these PLLs include frequency generation for audio and video decode/encode, interface standards, graphics processing, and network communications.

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