Product category:
Design and Development Software
News Release from: Monterey Design Systems | Subject: System-Driven Physical Design
Edited by the Electronicstalk Editorial
Team on 06 June 2001
Design methodology bridges gap to
fabrication
Monterey Design Systems describes System-Driven Physical Design as the first design methodology to enable physical chip implementation from system to GDSII tapeout of SoCs up to 100 million gates.
Monterey Design Systems describes its System-Driven Physical Design (SDPD) methodology as the first design methodology to enable physical chip implementation from system to GDSII tapeout of complex SoC designs as large as 100 million gates Created to address the growing gap between semiconductor fabrication capabilities and design capabilities, SDPD represents an innovative approach for physical implementation of complex leading-edge SoCs
This article was originally published on Electronicstalk on 10 Oct 2001 at 8.00am (UK)
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Hierarchical approach adds structure to design
Monterey Design Systems has announced version 2.2 of IC Wizard, the hierarchical design planner that drives its System-Driven Physical Design solution.
Timing analysis joins IC design planner
Monterey Design Systems has released version 2.3 of IC Wizard, the hierarchical design planner that drives the Monterey System-Driven Physical Design (SDPD) solution.
The SDPD methodology is the only design methodology that moves critical physical details to early planning stages - enabling a top-down constraint-driven approach that achieves predictable design closure much earlier than possible with previous methods.
With SDPD, design teams can plan, prototype, sign-off and implement their designs, all within a single, more productive flow.
"While other vendors are trying to develop integrated RTL to GDSII flows at the cell level, Monterey has gone a step beyond and moved physical consideration to the system level-providing a much more efficient and scaleable solution for the physical design of complex SoCs using deep submicron technologies", said Jacques Benkoski, president and CEO of Monterey Design Systems.
Further reading
SDPD solution pays off with tape-outs for Canon
Canon has taped out its first two designs with the Monterey System-Driven Physical Design (SDPD) solution.
Faster turnaround for submicron chip designs
Monterey Design Systems has released version 1.5 of Dolphin, its complete physical design solution.
IC Wizard does the trick for Morphics Technology
Fabless semiconductor company Morphics Technology has successfully completed multiple chips ranging from 5 to 15 million gates using Monterey's IC Wizard hierarchical design planner.
"By allowing system and logic designers to share physical awareness of area, timing and power constraints, design teams can optimize tradeoffs for chip implementations and rely on system constraints, driven top-down through detailed physical design, to achieve fast design convergence".
"LSI Logic is integrating Monterey's Dolphin and Sonar into its FlexStream Design System to boost the productivity of our designers.
We envision that the System-Driven Physical Design solution Monterey has built following the Aristo merger will significantly increase the productivity gain", said Christopher Hamlin, senior vice president, chief technology officer at LSI Logic.
"LSI Logic has extended its relationship with Monterey to promptly take advantage of this unique capability".
"System-Driven Physical Design is the reason and result of the merger between Monterey and Aristo", said Simon Bloch, executive vice president of Monterey and formerly president and CEO of Aristo.
"By combining our solutions, customers get the flow they have envisioned that includes top-level hierarchical design, physical prototyping with early sign-off and automated, predictable chip implementation.
This flow offers customers the most productive system for their designs today and well into the future".
Monterey is working closely with a number of customers who early on determined that merging the two companies would provide them with an improved design flow starting at the system-level.
The new benefits of increased productivity offered by SDPD will be demonstrated at the 38th Design Automation Conference in Las Vegas in June.
SDPD enables a design team to perform physical design in parallel with logic design and verification.
Consequently, system and logic designers have greater awareness of the physical impact of their decisions.
As a result, they are able to make more informed choices, more effectively optimising the design for area and timing to achieve performance and cost objectives within a predictable development time.
Monterey's integrated, yet open products enable SDPD with a design flow that reduces the number of tools required to achieve rapid physical design implementation of complex SoCs.
For system planning, IC Wizard provides hierarchical block-based physical design planning and chip implementation technology able to realize the smallest die size and highest performance for very large, complex designs.
In the SDPD flow, IC Wizard also generates the physical and timing constraints for subsequent block implementation using the customer's block-level implementation tools.
Sonar provides physical prototyping capability that allows a rapid validation of the design planning assumptions to achieve design closure.
Finally, Dolphin automatically implements the final layout of the individual blocks and full chip, achieving rapid, predictable design closure.
Sonar and Dolphin leverage Monterey's patented Global Design Technology, which solves the complex interdependencies among SoC design factors by simultaneously exploring all aspects of the physical design space to arrive at optimised solutions.
The entire solution provides sign-off at the design planning stage, followed by the In One Pass implementation of a manufacturing ready GDSII tape.
This methodology allows large teams of designers, geographically separated, to work on different pieces of a complex system-on-chip design, including IP and design reuse, to enable the fastest and most predictable time to market.
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