Product category:
Design and Development Software
News Release from: Monterey Design Systems
Edited by the Electronicstalk Editorial
Team on 20 June 2001
Monterey gathers its partners in
innovation
The Monterey Design Systems Partners in Innovation programme aims to bring together companies involved in IC development and ASIC design that have complementary and innovative technology.
The Monterey Design Systems Partners in Innovation programme aims to bring together companies involved in IC development and ASIC design that have complementary and innovative technology The mission of the programme is to foster design innovation and increase productivity through closer co-operation among partner companies
This article was originally published on Electronicstalk on 4 May 2001 at 8.00am (UK)
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Monterey Design Systems describes System-Driven Physical Design as the first design methodology to enable physical chip implementation from system to GDSII tapeout of SoCs up to 100 million gates.
"Monterey's tools provide an excellent solution that meets our requirements for speed, flexibility and cost savings that we would like to pass to our customers", stated Zvi Or-Bach, eASIC President and CEO.
"Forging a greater partnership through the Partners in Innovation program will allow us to integrate Monterey's IC Wizard, Sonar and Dolphin solutions with our eASICore to accelerate the design cycle and achieve faster turn-around for SoC and platform-based designs.
With this closer cooperation, ASIC designers will have the capability to reduce both design time and cost of deep submicron designs by using innovative logic configurable technology, while at the same time improving the design flow".
Further reading
Hierarchical approach adds structure to design
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IC Wizard does the trick for Morphics Technology
Fabless semiconductor company Morphics Technology has successfully completed multiple chips ranging from 5 to 15 million gates using Monterey's IC Wizard hierarchical design planner.
"Our partnership programme is unique in that we are selecting partners based on their innovative and forward looking methodologies and solutions rather than for pure business reasons", stated Bill Alexander, vice president of marketing for Monterey.
"Each member company has expressed an interest in supporting and developing solutions that will make our mutual customers more successful in the development of deep submicron IC designs using 0.18 micron and below geometries".
The program is divided into four parts: partners who provide design software; partners who are providers of the hardware and operating systems on which Monterey's software runs; partners who are suppliers of silicon and silicon services; and partners who provide libraries and library services.
Initial design software partners include Verplex, a supplier of tools and solutions for formal verification; Synplicity, a new entrant in the area of ASIC synthesis; eASIC, a supplier of firm and hard IP; and Sequence Design, a provider of tools for RTL/Architectural power estimation and analysis.
Prolific, a supplier of library compiler technology, joined the Partners in Innovation programme in the libraries and library services category.
An example of the co-operative efforts that will be encouraged by Monterey through its partners programme is the introduction of a high-productivity RTL to GDSII ASIC design flow intended to serve the high demand of FPGA and ASIC designers implementing cell-based designs.
The combination of Synplicity's new Synplify ASIC synthesis software, with Monterey's Sonar, the physical prototyping solution and Dolphin, the complete physical design solution, enables ASIC designers to achieve timing closure early in the design process and to shave months off the total design time.
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