Physical design technology is now patented

Monterey Design Systems has been issued patents numbered US 6,192,508 B1 and US 6,286,128 B1 by the United States Patent and Trademark Office.

Monterey Design Systems has been issued patents numbered US 6,192,508 B1 and US 6,286,128 B1 by the United States Patent and Trademark Office.

The patents, titled "Method for logic optimisation for improving timing and congestion during placement in integrated circuit design" and "method for design optimisation using logical and physical information", respectively, apply to the physical IC design technology that serves as the foundation for Monterey's Dolphin physical implementation product.

These patents cover Monterey's unique approach to the physical implementation of complex integrated circuits.

Monterey's simultaneous optimisation approach stands in sharp contrast to the more common sequential optimisation flow that breaks the physical implementation process into separate steps that must be iterated upon sequentially.

Commonly used sequential optimisation flows incorporating point tools for logic and physical synthesis, placement, routing, extraction, and analysis have become very convoluted.

These flows have been pieced together over time from new point tools and customised scripts as new requirements have arisen from advancing process technology.

Over the past five to ten years, sequential flows have become so unwieldy and fragile that they can no longer handle the volume of designs processed by large semiconductor companies.

The use of multiple tools in the design flow has caused significant problems for designers.

Each tool in the flow has a tendency to optimise using a different set of criteria.

Logic synthesis tools can optimise the timing, power, and area, but ignore physical considerations.

Placement tools optimise the placement of the cells while trying to meet timing constraints, but may not pay sufficient attention to routability.

Routing tools are given a problem to solve without any flexibility to change what has been done earlier in the flow, and thus may be asked to find a nonexistent solution.

Recent efforts to combine logic synthesis and placement have helped, but Montereyûs patented technology takes this approach much further.

By simultaneously optimising the logical structure, placement, and routing based on timing, area, and routability, Monterey's solution effectively eliminates the interoperability problems that occur when using many disparate tools.

"These patents are very significant because they give Monterey ownership of a technological approach that all physical design tools are evolving towards", said Jacques Benkoski, president and CEO of Monterey.

"Monterey's patented simultaneous optimisation technology allows our customers to streamline and simplify their flows so that they can easily handle hundreds of design starts per year".

The technologies protected by these patents are available today in Monterey's Sonar and Dolphin products, and as part of the company's System-Driven Physical Design solution on all supported hardware platforms.

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