Hierarchical design planner cuts chip size

Fujitsu has reported a big improvement in die size on a new chip design due to the early planning and analysis capabilities of the IC Wizard hierarchical design planner from Monterey Design Systems.

Fujitsu has reported a significant improvement in die size on a recently concluded chip design due to the early planning and analysis capabilities of the IC Wizard hierarchical design planner from Monterey Design Systems.

The chip, composed of 1.9 million logic gates and 125 memory blocks, was taped out on 30th October 2001.

"At Fujitsu, we are dedicated to physical hierarchical design methodology for large, complex ASIC designs", said Seiji Miyoshi of the System Circuit Technology Department, Communication Circuit and Device Technology Division, Transport Systems Group of Fujitsu.

"By using a new design methodology including IC Wizard, we were able to shrink the die size by more than our expectation".

"IC Wizard quickly and automatically generates multiple design plans enabling Fujitsu to evaluate different alternatives", said Rick Ader, General Manager of Asia Pacific Operations at Monterey.

"The power to explore several alternatives in such a quick fashion provided Fujitsu a new dimension in flexibility over developing their design plans manually as they have in the past".

On a chip design containing more than a hundred physical blocks, Fujitsu realised that it needed to automate its design plan methodology.

After examining a number of alternatives, it decided that IC Wizard would be a strong match for its requirements.

"IC Wizard was extremely useful as a design plan exploration tool", continued Miyoshi.

"We were able to quickly generate floorplans with IC Wizard that placed more than one hundred soft, hard, and memory blocks in a compact and physically efficient fashion, enabling us to reduce our original specification for the size of the die".

A number of features that Fujitsu found particularly useful included: the ability to quickly generate and evaluate multiple design plans; automatic block placement; automatic shaping of soft blocks; automatic port placement driven by the hierarchical global router that has full visibility through all levels of hierarchy; and hierarchy management tools that enable the user to manipulate the hierarchical structure at will.

Having an automated design planning solution resulted in improvements in turnaround time as well.

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