Two more patents for Monterey

Monterey Design Systems has been issued two patents by the US Patent and Trademark Office for its physical design technology, bringing its patent count to seven.

Monterey Design Systems has been issued two patents by the US Patent and Trademark Office for its physical design technology, bringing its patent count to seven.

Patent number US 6,367,051 is titled "System and method for concurrent buffer insertion and placement of logic gates" and patent number US 6,385,760 is titled "System and method for concurrent placement of gates and associated wiring".

Both these patents apply to the physical IC design technology that serves as the foundation for the Monterey Sonar physical prototyper and Dolphin physical implementation products.

In the past, buffer insertion has been performed as a separate operation after cell placement.

However, as process technologies advance towards 0.10um and beyond, the practice of inserting buffers after placement may cause congestion and routability issues that cannot be solved.

Operations such as extraction, analysis, logic optimisation, power and clock network construction and analysis, and buffer insertion must now be performed concurrently with placement and routing as part of an integrated implementation process rather than as afterthoughts.

These patents include the use of Monterey's continuous refinement and simultaneous optimisation approach to insert, and evaluate the effect of, buffers during placement and routing, rather than the more commonly used post-placement method.

Monterey's simultaneous optimisation approach, using an open cost function, is much better suited to achieving multiple objectives than the more common optimisation flow that breaks the physical implementation process into separate steps that must be performed sequentially through multiple iterations.

Commonly used sequential optimisation flows incorporating point tools for logic and physical synthesis, placement, routing, extraction, and analysis have become very convoluted.

These flows have been pieced together over time by adding new point tools and customised scripts to existing design flows as new requirements have arisen from advancing process technology.

Over the past five to ten years, sequential flows have become so unwieldy and fragile that they can no longer handle the volume of designs processed by large semiconductor companies.

The use of multiple tools in the design flow has caused significant problems for designers.

Each tool in the flow has a tendency to optimise using a different set of criteria.

Logic synthesis tools can optimise the timing, power, and area, but ignore physical considerations.

Placement tools optimise the placement of the cells while trying to meet timing constraints, but may not pay sufficient attention to routability.

Routing tools are given a problem to solve without any flexibility to change what has been done earlier in the flow, and thus may be asked to find a non-existent solution.

Recent efforts to combine logic synthesis and placement have helped, but Monterey's patented technology takes this approach much further.

By simultaneously optimising the logical structure, placement, and interconnect based on timing, area, and routability, Monterey's solution effectively eliminates the interoperability problems that occur when using many disparate tools.

"Monterey has always been known for technological excellence and a conceptually superior approach to physical implementation", said Jacques Benkoski, president and CEO of Monterey.

"As the challenges for designing faster and smaller continue to mount, we believe that the industry will continue to gravitate towards our approach, and having these patents gives Monterey a big advantage over the competition".

The technologies protected by these patents are available today in Monterey's Sonar and Dolphin products, and as part of the company's System-Driven Physical Design solution, on all supported hardware platforms.

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