Capacity and accuracy boost RTL-to-GDSII solution

Dolphin RTL is a second-generation RTL-to-GDSII solution, and the culmination of an 18-month collaborative effort between Monterey and Synplicity.

Dolphin RTL is a second-generation RTL-to-GDSII solution, and the culmination of an 18-month collaborative effort between Monterey and Synplicity.

Dolphin RTL blends RTL reader and logic structure generation technology from Synplicity with comprehensive physical synthesis capabilities from Dolphin into a unified solution.

It uses Synplify ASIC technology to quickly generate an initial logic structure independent of wire loads and then performs tech mapping and logic optimisation using patented Monterey Progressive Multi-objective Refinement (PMR) technology to meet timing and other design constraints.

First generation RTL-to-GDSII tools use placement information during synthesis to predict wire delays during optimisation.

Although this approach provides advantages over old-style wire-load model synthesis, it still has insufficient wire modelling accuracy to handle the requirements of nanometer designs.

First generation RTL-to-GDSII tools also suffer from limited capacity, which severely limits their usefulness.

Dolphin RTL, the second generation RTL-to-GDSII solution from Monterey, is the first RTL-to-GDSII tool that provides the accuracy and capacity needed to handle nanometer designs.

One of the most glaring weaknesses of first generation RTL-to-GDSII solutions is their inability to account for clock trees and power networks during physical synthesis and placement.

Older physical synthesis tools ignored power and clock, which effectively pushed these critical elements deep into the back end of the physical implementation process, after placement.

Attempting to add power and clocks as a post process often required major reconstructive efforts and often, the process would have to be restarted from scratch with an unplaced netlist.

Dolphin RTL resolves this by performing all physical synthesis, implementation, and analysis operations simultaneously, including logic optimisation, power network construction, placement, clock tree synthesis, and routing.

In addition, Dolphin RTL simultaneously optimises the design to meet all requirements timing, power, clock, die size, routability, and signal integrity.

It achieves this by using a multi-objective cost function during optimisation.

Only in this way can total design closure be achieved on designs implemented with the most advanced process technologies.

First-generation RTL-to-GDSII solutions suffered from limited capacity.

Large designs would be divided into manageable partitions containing 50-150K gates.

However, the interconnectivity between the partitions often caused timing violations and high levels of routing congestion.

As a result, many iterations were needed to achieve design closure on timing, area, and routability.

Both the Synplicity Synplify ASIC synthesis solution and Monterey Dolphin physical implementation system are renowned for being able to handle flat multi-million-gate designs.

Dolphin RTL capitalises on this by offering a complete RTL-to-GDSII solution that can handle 2 million flat gates and more.

"Dolphin RTL is the only second generation RTL-to-GDSII system available today", said Enno Wein, product marketing director at Monterey.

"Accuracy and capacity are the keys to design closure on current and future generation process technologies.

Dolphin RTL is the most accurate and highest capacity solution on the market today".

Dolphin RTL will be available in November 2002 on all supported hardware platforms.

Pricing starts at $460,000 per year (US price).

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