Programme cuts costs of customer-owned tooling

Monterey Design Systems has set up a co-operative programme aimed at reducing the cost of adoption for IC designers seeking to perform in-house physical implementation of their chips.

Monterey Design Systems has set up a co-operative programme aimed at reducing the cost of adoption for IC designers seeking to perform in-house physical implementation of their chips.

Leading providers of EDA tools, libraries, semiconductor intellectual property (SIP), foundries, design services, and compute platforms are working together to reduce the time and effort required to establish an in-house customer-owned tooling (COT) flow.

"We have already benefited from cooperative efforts between the members of the Total COT programme", said Gideon Paul, Vice-President of Research and Development at TeraChip.

"We consider our in-house COT flow to be an integral part of our competitive strategy.

Design issues that require interaction between the logical and physical design teams used to take days or weeks to resolve.

Having the physical design team in-house allows us to resolve these issues in hours or even minutes".

"Chip designers today are adopting in-house COT design flows for a number of reasons - performance, cost and turnaround time", said Tom Kozas, Director of Business Development at Monterey Design Systems.

"The Total COT programme allows customers to reap these advantages while reducing the cost and risk associated with developing and implementing a COT physical design flow".

Developing and implementing a production physical design flow can be a very costly and time-consuming process.

The Total COT programme reduces ramp-up time and cost by bringing together component technologies to form a comprehensive solution.

The compatibility of these component technologies is prevalidated by completing reference designs using specific EDA tools, libraries, SIP, and foundry processes on specific compute platforms.

This ensures working solutions and minimises the risk of adopting COT physical design flows.

Co-operating companies in the programme include ARC International, Artisan Components, Astek Corp, Genesys Testware, GoFabless.com, Monterey Design Systems, Nassda Corp, Red Hat, Synplicity, Tower Semiconductor, Verplex Systems and Virtual Silicon Technology.

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