Toolset speeds digital interface chip development

Acuid Corp has purchased the entire suite of Monterey design tools for use on chips with ultra-high bandwidth interfaces (above 100Gbit/s).

Acuid Corp has purchased the entire suite of Monterey design tools for use on chips with ultra-high bandwidth interfaces (above 100Gbit/s).

The toolset consisting of the IC Wizard hierarchical design planner, Sonar physical synthesis and prototyper, and Dolphin physical implementation system will completely displace Acuid's existing toolset and become the basis for the standard IC design flow at Acuid's design centre in St Petersburg, Russia.

Streamline Design Solutions, Monterey's sole distributor in Russia, worked closely with Acuid to validate the capabilities of the Monterey tools and will continue to provide technical support to Acuid.

"With our previous design flow, we were experiencing serious tool deficiencies that made it very difficult to achieve timing closure on the standard digital logic sections of the chips", said Dr Alex Deas, President of Acuid Corp.

"Timing closure required an unpredictable number of layout loops, and had a severe impact on our ability to forecast tapeout schedules accurately.

The decision to change to Monterey tools solves these problems and allows us to implement complex designs in a small fraction of the cost and lead time required by our previous design flow".

Acuid's technology allows the company to provide high-speed digital interfaces where each signal pin can run at over 28Gbit/s - ten times that of Acuid's nearest competitors in commodity CMOS processes.

Acuid engineers are integrating these high-speed interfaces with memory, processor cores, and 10 Gigabit Ethernet (10GbE) to produce products such as 10GbE XFP to PCI chips.

Within the chips, the internal clock speed slows considerably due to the deserialisation of the signals onto wide, multibit buses.

Using the Monterey tools instead of their previous design flow, Acuid believes that it will be able to double the internal clock speed of its chips without sacrificing schedule predictability.

This greatly simplifies the task of interfacing the high-speed ports with the slower internal logic and is a direct benefit of the planning and accurate prototyping capabilities offered by the Monterey tools.

As part of its evaluation process, Acuid chose a 10GbE design containing a data formatter soft block running at 400MHz.

Engineers ran the design through both their existing design flow and through the new Monterey flow.

The legacy design flow was unable to close timing on the block, producing a result with 300ps of negative slack.

The engineers estimated that it would take one month to perform the manual edits required to achieve timing closure.

In contrast, the Monterey tools achieved timing closure in one hour, producing a result with 90ps of positive slack.

In addition, the Monterey tools provided feedback on crosstalk, which was not available from the displaced toolset.

"After careful consideration of all available options, we chose Monterey because its tools provide us with the accurate prototyping and predictable design closure that we need", concluded Deas.

"We believe that Russia will grow to be a very large and strategically important market for EDA technology", said Johnny Thunborg, President of Streamline Design Solutions.

"The pool of design expertise here is growing very rapidly and the demand for the most advanced technology, such as the Monterey toolset, is virtually limitless".

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