Design planner qualified for Blue Logic

The Monterey design planner has been qualified for inclusion in IBM's Blue Logic standard ASIC design methodology.

The Monterey design planner, which incorporates the company's patented Progressive Refinement technology, has been qualified for inclusion in IBM's Blue Logic standard ASIC design methodology.

As part of the IBM Blue Logic flow, the Monterey design planner starts the silicon virtual prototyping process by automatically placing the large macros.

The resulting floorplan continues through the IBM Blue Logic methodology, until the final physical implementation is complete.

Qualification work for Monterey's prototyper (Sonar) is also in process.

IBM conducted an evaluation of the Monterey products using a test chip containing 1.5 million gates and over 200 large macrocells using IBM's 130nm process technology.

The chip-level design plan was completed in less than an hour using the Monterey design planner to automatically place all of the blocks and to optimise the hierarchy for final implementation.

As part of the IBM Blue Logic methodology, the Monterey design planner will be made available to all IBM Microelectronics ASIC design centres and their customers.

"Widespread adoption and usage of our products at IBM is a major milestone for Monterey", said Jacques Benkoski, President and CEO of Monterey.

"Rather than a culmination, we view this as the beginning of the next stage of our ongoing partnership and look forward to a long and mutually beneficial association with IBM and their customers".

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