Virtual prototyper boosts design productivity

The Calypso silicon virtual prototyping (SVP) system is built on a foundation of patented Monterey Progressive Refinement technology.

The Calypso silicon virtual prototyping (SVP) system is built on a foundation of patented Monterey Progressive Refinement technology.

Calypso is the first SVP system to include both hierarchical design planning and physical prototyping in a single tool.

Calypso equips the design team to make informed decisions on critical high-impact design decisions very early in the design cycle.

"The biggest source of untapped productivity and quality improvements is in the interaction between the front-end and back-end design teams", said Dave Reed, Vice President of Marketing at Monterey.

"Calypso bridges this gap by enabling designers to see the physical impact of their architectural choices by efficiently automating pre-RTL physical design", he added.

Design problems that could result in months of painful physical implementation work to achieve timing closure can be recognised in hours and can often be addressed with very simple design changes.

Calypso combines hierarchical design planning, physical synthesis, and physical prototyping in a single tool built on top of a hierarchical database.

This enables capabilities that were not previously available in any tool or any combination of tools.

For example, it is now possible to quickly optimise the timing of a path that spans multiple blocks without having to go into each individual block and optimise each sub-path contained within the timing path.

Calypso also enables instantaneous incremental analysis.

For example, if a power rail is widened at the chip level, Calypso can instantly and incrementally measure the effect on IR drop inside all of the blocks.

In this same way, all planning and prototyping operations are now hierarchical and incremental - timing analysis and optimisation, clock tree synthesis, IR drop analysis, block placement, port optimisation, antenna fixing, and global routing.

Beta customers have used Calypso's hierarchical design planning and prototyping capabilities to produce chips that have achieved a range of improvements, such as 30% smaller, 15% faster, and costing 10% less to manufacture than customers could have achieved without Calypso planning and prototyping.

Design plans and detailed prototypes providing feedback on timing, power consumption, die size, and cost have been completed on multi-million gate chips in less than a day.

"Early customer response to Calypso has been phenomenal", said Jacques Benkoski, President and CEO at Monterey Design.

"Even companies who have no budget for conventional EDA tools are finding ways to purchase Calypso.

Seven of the top ten semiconductor companies in the world have been using beta versions of Calypso with great success and are eagerly awaiting the product release".

The initial release of Calypso will be shipped to customers starting in September 2003.

It will be supported on Unix and Linux workstations.

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