Programme takes physical IC design to new level

The Monterey Calypso Vanguard programme aims to address the rising cost of designing multi-million-gate chips and the severe penalties of making uninformed decisions early in the design cycle.

The Monterey Calypso Vanguard programme aims to address the rising cost of designing multi-million-gate chips and the severe penalties of making uninformed decisions early in the design cycle.

"The economic paradigm has shifted dramatically and upped the ante in the IC design world", said Jacques Benkoski, President and CEO of Monterey.

"The ability to see from the beginning of the design the impact of all the decisions from architecture to process is critical to the success of the product, or sometimes of an entire business segment.

Wrong early decisions can never get recouped later".

The Monterey Calypso Vanguard programme is designed to equip its members with the technology and methodologies that will provide them with the critical information that they need to make the right decisions early in the design cycle, such as the choice of process technology, choice of IP blocks, architecture, power and clocking schemes, and chip-level design plan.

The programme was designed for companies that are developing multi-million-gate chips and view the Progressive Refinement methodology as a key competitive differentiator.

Member companies are seeking an integrated physical design solution where planning and prototyping enable early exploration of critical design alternatives.

The benefits include faster, more predictable design cycles, and the early availability of information that enables them to make high-impact decisions on an informed basis.

The programme provides members with early access to Monterey's patented Progressive Refinement technology and future products.

This allows member companies to validate the compatibility of their IP elements with the Monterey technology.

Charter members include Toshiba, Ricoh and Fujitsu.

"There are many conflicting requirements in the planning and prototyping process of complex SoC designs.

Maximum frequency, die size, numbers of metal layers, and process margin (yield) are largely determined in this key phase in the design cycle", said Tohru Furuyama, General Manager of the SoC Research and Development Centre of Toshiba.

"Monterey gives us early visibility as to the timing, power consumption, and most importantly the cost of the chip.

With this information, we can judge whether or not the SoC will meet the requirement of the end application and adjust the design if necessary".

"At 130 nanometres and below, conventional design flows are very unreliable, in that we can get all the way to the end of the flow and still not have a chip that meets all of our requirements", said Zenji Oka, Manager of the CAD Engineering Section, Image System LSI Development Centre at Ricoh.

"The Monterey Progressive Refinement methodology gives us accurate physical information early enough in the process that we can fix the problem by changing the design, rather than the much more difficult task of trying to fix it later during final physical implementation".

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