Two more patents for Monterey

Monterey Design Systems has been issued two new patents by the United States Patent and Trademark Office, bringing the company's patent total to 14.

Monterey Design Systems has been issued two new patents - "Method for design optimisation using logical and physical information" (US 6,557,145) and "Method for designing large standard-cell based integrated circuits" (US 6,567,967) - by the United States Patent and Trademark Office, bringing the company's patent total to 14.

The patents apply to the silicon virtual prototyping and physical implementation technology that enables the Monterey Progressive Refinement approach for multi-million-gate nanometre chips.

The silicon virtual prototyping patent applies to an automated method of designing large digital integrated circuits by partitioning the design into physically realisable partitions and then creating the connections between the partitions so as to maximise performance and routability while minimising the die size.

Timing and physical constraints are generated for each partition and passed on to a physical implementation tool.

The partitions are then placed and routed independently as if each were a separate circuit.

The physical implementation patent covers a method for design optimisation using logical and physical information by simultaneously performing logic optimisation and placement using an open multi-objective cost function.

The method can further accommodate routing optimisation by including an additional term into the cost function.

The patented technology is incorporated in the company's recently announced Calypso product - the first complete silicon virtual prototyper and Dolphin physical implementation system.

Calypso is the first product that combines hierarchical design planning together with fast, accurate silicon performance estimation in a single integrated tool.

Dolphin implementation provides a streamlined path from RTL to GDSII.

Together, they address all design requirements in a smoothly progressive flow from the beginning of the design process to final tapeout.

As the cost of design rises exponentially with each new generation of process technology, the penalty of making a bad decision early in the design cycle becomes increasingly severe the classic example being choice of process technology.

Monterey's Progressive Refinement technology provides design teams with valuable information about the final physical implementation very early in the design cycle.

With Monterey planning, prototyping, and implementation tools, the design team can very quickly develop accurate trial implementations of critical parts of the chip, and determine whether all design requirements can be met using a specific process.

In this way, design teams may discover they can use a less expensive, higher-yielding process and save millions of dollars that could have been lost using a more advanced process, due to higher mask set and manufacturing costs or poor yields.

IBM Microelectronics recently qualified the Monterey hierarchical design planner for use as part of the Blue Logic standard ASIC design methodology that is used in all of IBM's ASIC design centres worldwide.

The Monterey Progressive Refinement approach enabled STMicroelectronics to get accurate feedback on the final physical implementation of an eight-million-gate, two-chip set-top-box controller far in advance of completing the physical layout.

This information enabled them to optimise the architectural and logic design to produce a faster, denser chip set in less time than with their previous design flow.

Using Monterey products, Toshiba Corporation, a Calypso beta customer, was able to construct and evaluate 30 different global power networks on a 3.9-million-gate chip in less than two weeks.

Fujitsu, another Calypso beta customer, was able to simultaneously explore multiple chip-level design plans on a 3.3-million-gate chip containing over 300 memory macros.

The resulting chip was 15% smaller than it would have been without Progressive Refinement.

The implementation technology covered by these patents is available today in the Dolphin physical implementation system.

Much of the silicon virtual prototyping technology is available today in the current design planning and physical prototyping products.

The full spectrum of patented technology will be available in the initial release of the Calypso silicon virtual prototyper in September 2003.

Back to top