Virtual prototyping speeds Toshiba to tape-out

Toshiba Corporation has completed a multimedia SoC design using the Monterey silicon virtual prototyping (SVP) tool suite.

Toshiba Corporation has completed a multimedia SoC design using the Monterey silicon virtual prototyping (SVP) tool suite.

Physical hierarchy was required due to the complexity of the chip, which contains multiple media embedded processor (MeP) modules - Toshiba's embedded processor core targeting the digital consumer market.

The design was manufactured using Toshiba's 0.13-micron, six-metal-layer process, and first silicon prototypes are functioning correctly in the test lab.

The design contains 8 million gates, 151 large macro blocks, 33 clocks with the fastest clock running at 266MHz.

The completion of this production design comes on the heels of a 3.9 million gate 0.18-micron validation design completed by Toshiba earlier this year.

"The Monterey silicon virtual prototyping tools provided early physical information on many critical metrics that helped us refine the architecture and optimise the logic for physical implementation", said Tohru Furuyama, General Manager of the SoC Research and Development Centre of Toshiba.

"The Monterey products enabled us to determine the best partitioning for the standard cell blocks, as well as their shapes and locations.

We used the top-level design plan to drive port and feedthrough generation on the partitions and the placement of the standard cells within the blocks.

We were also able to minimise the die size by determining the best hard macro placement and configuration with the Monterey design planning and analysis capabilities".

On this design, Toshiba employed a hierarchical partitioning technique where connectivity between the partitions is achieved by abutment, without the use of routing channels.

Using the Monterey design planner, 70 logic modules were grouped into seven physical partitions without changing the logical hierarchical structure of the original netlist.

Preserving the logical structure of the netlist reduced the time and effort required for physical verification.

Toshiba found the early feedback on physical parameters to be very useful in optimising the design plan and minimising die size.

"We are very proud to be able to make a strong contribution in the planning and prototyping of this MeP-based SoC.

The Monterey solution provides the hierarchical planning and physical prototyping functionality that enables Toshiba to explore many high-level design alternatives", said Rick Ader, General Manager of Japan and Asia Operations at Monterey.

"By using the Monterey SVP tools, Toshiba is able to solve problems by adjusting the architecture and logic problems that would be impossible to repair later during physical implementation.

Monterey's SVP tool suite enabled Toshiba to start with a preliminary netlist, place the Verilog modules, and provide guidance to create the physical partitions for detailed implementation.

This information was fed back to front-end designers as the RTL was being written.

As a result, the logical hierarchy of the design matched the physical design, which greatly eased verification.

Also, having early physical feedback allowed the design team to fix problems during the coding of the RTL problems that might have been impossible to resolve later in the process during physical implementation.

According to Toshiba, this is a very unique capability of the Monterey design planner and was used extensively during the physical design process.

Placing the ports connecting abutting partitions is crucial to performance and avoiding potential signal integrity problems downstream.

Port placement that is driven by global routing improves performance by minimising wire length and reduces the potential for signal integrity violations by minimising routing congestion at the partition boundaries.

The Monterey SVP tool offers hierarchical, global-route-driven port placement, which according to Toshiba, is available only from Monterey.

Toshiba worked with Monterey to utilise the early IR drop analysis capabilities of the Monterey SVP tool.

IR drop was measured both at the chip-level and within the blocks of the design.

This allowed them to quickly converge on the physical structure of the global power network.

The early phase IR drop analysis allowed for the "freezing" of the top-down driven floorplan to occur at as early a physical design stage as possible.

Toshiba maintains a rich library of hard macros, many of which have multiple versions from which to choose.

On a design containing 151 hard macros, it would take countless trial-and-error iterations to develop a good top-level plan.

Toshiba took advantage of the automatic design planning features of the Monterey SVP tool to automatically place the hard macros, and then interactively substitute alternate versions of those macros to further optimise the design plan.

These substitutions were achieved without the need to edit the netlist.

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