Novel technology shrinks MPEG2 codec chip die

To meet the low cost requirements of high volume markets, Toshiba turned to AFP technology to reduce the die size of its eight million gate design by 10.5%.

In the evolving world of IC design and manufacturing, the ability to design consumer electronics and sell them in high volume at a profit is an elusive target for many semiconductor companies.

Of the various approaches to lower cost, die size reduction through design optimisation is by far the most valuable weapon.

When the die size of a chip is reduced, the laws of physics and economics align.

Shorter wires generally produce better timing and reduced power consumption.

With a smaller die, the raw number of die per wafer increases.

Area related yield losses are thereby diminished, resulting in a significantly lower cost per known good die.

The cost reduction is almost quadratic; on a 90mm2 design produced in a 0.13um process with a volume of 10 million units, a 10% die size reduction results in a cost reduction of $20 million by some estimates.

For chips targeted for high volume markets such as consumer electronics, a respin focused on die size reduction is typically attempted once the initial design reaches volume production.

Many designers attempt the die size shrink respins through a long and expensive re-architecting of the chip at a functional or behavioural level based on the experience gained in completing the initial design.

There is a much more straightforward approach: take the existing design data - the synthesised netlist, hard IP, and physical process and library information - and build the most compact, efficient chip that is physically possible.

Using AFP Technology from Monterey Design Systems, this approach was put to the test on Toshiba's MeP (Media embedded Processor) MPEG2 codec project, a 0.13um, eight-million-gate consumer electronics design.

The secret to a smaller die without re-architecting the entire chip is an efficient hard macro placement that creates a smooth data flow in the chip and allows the cell placement to reach a higher utilisation without encountering congestion.

Using AFP technology, the natural data flow in the design is extracted and is used to drive an automatic placement of the hard macros.

Such designs can achieve cell utilisation of 80 to 90%.

One of the telltale signs that AFP technology has been applied to a design is the nontraditional (and frequently nonintuitive) placement of the hard macros.

They are placed based on the design's data flow, often in the centre of a block.

Shrinking Toshiba's MPEG2 codec design posed two significant challenges: the original chip was implemented hierarchically using nine physical partitions in a channel-less (abutting) top-level floorplan.

Hard macro placement in each of these physical partitions was on a block-by-block basis.

Toshiba established an aggressive goal of shrinking the core area of this design by at least 10% from its original size.

Two approaches were considered to meet this goal: create completely new physical partitions based on a "flat" placement of the hard macros; or retain the physical partitions from the original floorplan, adjusting their sizes and shapes while still maintaining a channel-less top-level structure.

AFP technology block placement and partitioning features support both these approaches.

Even though the first approach results in a smaller die size, the final choice was to use the second approach.

This decision was primarily driven by the large impact that a physical partitioning change can have on the front-end design and off-chip interfaces.

AFP technology can be used to view the entire chip "flat" and deliver optimised hard macro placement within the chip context.

Then designers can partition as they see fit based on this placement.

AFP technology can also be applied within each block, generating optimal macro cell placement within the block while taking into consideration the macros that the block will need to communicate with in adjacent blocks - an approach called "transparent block placement".

In the case of Toshiba's MPEG2 codec design, the positions of several of the hard IPs - such as the PLL, DAC, USB and macros in the DDR interface block - were relatively "fixed" due to off-chip communication.

Hence, the die-size reduction of this design was achieved by keeping within the partitions of the original chip.

AFP technology had to shrink eight of the nine partitions in order to achieve a 10% reduction in core size.

AFP technology was applied in a fully hierarchical form in a highly constrained situation.

Despite those constraints, area reductions of the standard cell parts of the blocks ranged from a minimum of 10% on Block 7 and up to 41% on Block 6, with an average reduction of 24% of the standard cell areas.

The designers decided not to shrink Block 9 which contained the high speed DDR interfaces and consisted of a narrow shape adjacent to the right-side I/Os.

The resulting block floorplans were fully placed and routed and easily achieved full design closure.

The final chip was reassembled from the blocks and achieved full design closure.

The final layout delivered a 10.52% core reduction, enabling the design team to reach the cost targets.

Toshiba applied Monterey's new AFP technology to plan the design of a cost-sensitive consumer electronics chip of eight million gates.

This enabled the company to reduce the die size by more than 10%, thereby achieving critical cost milestones.

This result was achieved without having to change the chip functional description, the IP, the libraries, or the back-end physical design flow.

The resulting design easily achieved design closure.

Following the successful application of this new approach, Toshiba is now applying the AFP technology on a low power production design in its Multi-Media Business Unit.

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