MoSys verifies 1T-SRAM on 0.13-micron process

MoSys has completed silicon verification of its ultra-dense 1T-SRAM embedded memory technology on TSMC's 0.13-micron standard logic process.

MoSys has completed silicon verification of its ultra-dense 1T-SRAM embedded memory technology on TSMC's 0.13-micron standard logic process.

The patented ultra-dense memory technology delivers dramatic production benefits in cost and yield compared to traditional six transistor embedded SRAM and is now silicon-proven for the latest generation logic process.

As designers are increasingly challenged by requirements for high reliability combined with lowest cost, 1T-SRAM memory technology delivers a measured soft error rate of 1000FITs/Mbit that is more than an order of magnitude better than six transistor SRAM at the 0.13-micron process generation.

As a result, designers may be able to avoid using costly error correction techniques that may be required by applications using traditional SRAM on the same process.

"1T-SRAM embedded memory is already proven in volume production using three earlier process generations and is now available on the 0.13-micron process; the choice for next generation products", commented Mark-Eric Jones, MoSys' vice president and general manager of intellectual property.

"It is also demonstrating superior reliability and scalability as process technology advances to finer geometries".

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