Product category:
Memory Devices and Modules
News Release from: MoSys | Subject: MC8051M36
Edited by the Electronicstalk Editorial
Team on 09 October 2001
36Mbit SRAM is optimised for 100% bus
usage
MoSys is shipping its high-density, low-power 36Mbit memory, making it the first to market with this level of bit density.
MoSys is shipping its high-density, low-power 36Mbit memory, making it the first to market with this level of bit density The MoSys SRAM is aimed at high-end data, telecommunications and DSP applications
This article was originally published on Electronicstalk on 21 Aug 2001 at 8.00am (UK)
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Off-the-shelf macros put 1T-SRAM on SoC menu
MoSys has made available a family of standard 1T-SRAM memory macros using silicon-proven 0.25- and 0.18-micron cores.
The new 36Mbit MC8051M36 symmetric pipelined burst SRAM is designed for 1.8V memory core power and either 1.8 or 2.5V I/O power.
The MC8051M36 symmetric pipelined burst devices operate at speeds up to 200MHz, with sub-3ns clock to data access time.
MoSys' industry-leading 36Mbit SRAM offers the highest available bit density and lowest power consumption.
"By using MoSys' unique technology, this product offers designers the best possible use of system space and power", said Andre Hassan, MoSys' vice president and general manager of memory products.
"MoSys will continue to build on its technology leadership by developing and offering even higher density SRAM products".
The MC8051M36 SRAM's symmetric read and write pipeline timing is optimised for 100% bus usage.
Eliminating the bus turnaround cycles required by SRAMs with different read and write pipeline delays is essential for today's high-end equipment.
The MC8051M36 symmetric pipelined burst SRAM is currently sampling in industry standard 100-pin LQFP package.
Production quantities will be available in November.
The MC8051M36-7R5 is priced at $100.10 in 1000-piece quantities.
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