Second-generation 1T-SRAM saves even more power

MoSys and Taiwan Semiconductor Manufacturing Company (TSMC) have successfully implemented MoSys' second-generation 1T-SRAM technology optimised for very low-power mobile applications.

MoSys and Taiwan Semiconductor Manufacturing Company (TSMC) have successfully implemented MoSys' second-generation 1T-SRAM technology optimised for very low-power mobile applications.

The first generation 1T-SRAM technology has been successfully deployed in volume production of low-power consumer applications.

Now the second-generation 1T-SRAM technology challenges even the data-retaining standby power capabilities of 6T SRAM, with standby current capabilities of just 10uA/Mbit or less when implemented in TSMC 0.13-micron logic processes.

Dr Fu-Chieh Hsu, MoSys CEO, stated: "Over the last two years, MoSys has consistently demonstrated the many fundamental advantages of our patented, embedded 1T-SRAM technology over traditional 6T SRAM and embedded DRAM.

Every one of our licensees' products embedding 1T-SRAM has been developed successfully achieving better manufacturing yield and time-to-volume than traditional technologies.

We have clearly demonstrated that 1T-SRAM has far superior soft-error-rate (SER) reliability than 6T SRAM starting at the 0.15-micron process node and our reliability figures-of-merit are now orders of magnitude better on the 0.13-micron process node and beyond.

We are very pleased to show in alliance with TSMC yet another fundamental advantage of our 1T-SRAM technology in consuming much less standby power than traditional 6T SRAM while retaining full data content".

Genda Hu, Vice President of Marketing at TSMC, added "TSMC has worked very closely with MoSys to deliver logic processes especially optimised for improving 1T-SRAM characteristics, including power dissipation.

We are committed to offering our customers the most manufacturable and competitive solutions for their SoC products with embedded memories".

Traditional 6T SRAM suffers from the fundamental CMOS scaling limit of subthreshold voltage, which must be a small fraction of the supply voltage.

As advanced logic processes progress to 0.13-micron and below, the supply voltage is reduced to 1.2V or lower.

To maintain device performance, the threshold voltages are also lowered which causes all transistors to leak even when there is no circuit switching.

As 6T SRAM uses six transistors in a crosscoupled configuration, there are at least three transistors leaking across the supply rails for each memory bit cell and progressively more through the gate oxide.

For today's large embedded memories, the overall leakage current accumulates to unacceptably high levels and is worsening with every advance in process geometry.

MoSys' patented 1T-SRAM memory cell is fundamentally immune to this scaling problem because there is no direct leakage path across the supply rails in each memory bit cell while oxide leakage is easily suppressed.

Coupled with advanced and patented circuit techniques and proprietary memory cell configuration to suppress the high natural leakage currents of standard logic processes, MoSys' 1T-SRAM technology now delivers lower standby current than 6T SRAM using the same logic processes.

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