Product category:
Intellectual Property Cores
News Release from: MoSys
Edited by the Electronicstalk Editorial
Team on 18 January 2002
MoSys turns to Mentor to reduce memory
test costs
MoSys and Mentor Graphics are working to qualify and deliver memory built-in self-test (BIST) solutions optimised for the MoSys 1T-SRAM family of high-density embedded memories to reduce test cost.
MoSys and Mentor Graphics are working to qualify and deliver memory built-in self-test (BIST) solutions optimised for the MoSys 1T-SRAM family of high-density embedded memories to reduce test cost MoSys and Mentor have verified the integration of 1T-SRAM embedded memories using the Mentor Graphics) MBISTArchitect and BSDArchitect tool suites for memory BIST and boundary scan, respectively
This article was originally published on Electronicstalk on 21 Aug 2001 at 8.00am (UK)
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By leveraging the Full-Speed capabilities within the MBISTArchitect tool, this collaboration between industry leading technologies in DFT and embedded memory demonstrates an effective method for reducing test costs while maintaining high product quality.
More than an interoperability effort, MoSys and Mentor have formed this strategic alliance to identify and implement new capabilities within the MBISTArchitect tool to test and qualify embedded memories developed by MoSys.
The first results of this effort will be available in early 2002 in the form of additional features to support the various 1T-SRAM interface modes.
Additional capabilities to support on-chip memory repair analysis for improved yield will follow.
"Reducing test costs while ensuring product quality has always been a mantra for Mentor Graphics DFT and this alliance with MoSys enables us to achieve these same goals for our mutual customers", said Lori Watrous-deVersterre, general manager, Design-for-Test, Mentor Graphics.
"By incorporating the Full-Speed capabilities of our MBISTArchitect tool, MoSys can continue to provide customers with high quality embedded memories for use in system-on-chip designs".
"We are proud to be working with Mentor Graphics on integrating 1T-SRAM embedded memories with Mentor Graphics' DFT tools", said Mark-Eric Jones, Vice President and General Manager of Intellectual Property at MoSys.
"By optimising the memory BIST controller design to support 1T-SRAM memories, Mentor Graphics will be able to reduce the test time, thereby providing cost benefits to our customers in addition to the high density and manufacturability of our technology.
The ongoing co-operation regarding on-chip repair analysis will further benefit our mutual customers".
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