Folded capacitors redouble embedded SRAM density

MoSys has released its 1T-SRAM-Q (quad density) technology which it reckons achieves four times the density of traditional SRAMs.

MoSys has released its 1T-SRAM-Q (quad density) technology which it reckons achieves four times the density of traditional SRAMs.

This addition to the 1T-SRAM technology addresses the industry's need for increasing memory density.

The market demands for lower power in consumer products and greater bandwidth in high performance products are driving the need for more on-chip memory.

By combining MoSys' proven 1T-SRAM technology with its new folded area capacitor (FAC), the company has created the solution with 1T-SRAM-Q technology, doubling the density of 1T-SRAM memory.

1T-SRAM memory requires a single, noncritical mask addition to industry standard CMOS logic processes adding no more than 5% to the wafer processing cost.

"By introducing the 1T-SRAM-Q technology, MoSys has solidified its leadership position as an innovative supplier of memory in the embedded marketplace", commented Sherry Garber, Senior Vice President of Memory Products, Semico Research Corporation.

"MoSys has recognised the need for higher density, lower power, embedded memory, combined with error correction features that could be fabbed on widely available logic processes.

This is a product positioned for rapid adoption".

Building on the proven 1T-SRAM-RB technology, 1T-SRAM-Q memory includes MoSys' Transparent Error Correctiont (TEC ) offering the benefits of eliminating laser repair, improving yield, reliability and soft error rate while doubling the density.

The reduced area of 1T-SRAM-Q memory results in shorter internal signal paths thereby increasing the speed and lowering power consumption.

"Three years ago, MoSys launched its proprietary 1T-SRAM technology which doubled the density of embedded memory on standard logic processes.

As anticipated, the market has continued to require even more on-chip memory and once again, with 1T-SRAM-Q, MoSys is delivering the technology, to address this need", stated Dr Fu-Chieh Hsu, President and CEO of MoSys.

"By leveraging the manufacturability of standard logic processes in combination with our production proven 1T-SRAM architecture, MoSys continues its commitment to our customers by delivering innovative embedded memory technologies required by SoC designers".

MoSys' patented folded area capacitor technology reduces bit cell size by literally folding the 1T-SRAM gate oxide capacitor vertically down the STI sidewall so that it occupies less horizontal die area.

The resulting bit cell sizes of 0.50 and 0.28um2 enable 1T-SRAM-Q memory to be used for integrating up to 128 or 256Mbit of embedded memory in 130 and 90nm processes, respectively.

This is achieved by using only one additional noncritical mask in the standard logic process.

Most significantly, the additional processing does not add to the transistor thermal cycle, resulting in no change to the logic transistor characteristics.

This avoids the need to recharacterise existing logic IP for integration in SoCs using 1T-SRAM-Q memory technology.

Licence and NRE pricing for designers using 1T-SRAM-Q memory will remain the same as existing 1T-SRAM technology.

MoSys is currently engaged with initial adopters of 1T-SRAM-Q technology for expected sampling in 2Q 2003 and mass production late 2003.

(This was Electronicstalk's Top Story on 18 December 2002).

(This was Electronicstalk's Top Story on 18 December 2002).

Back to top