SRAMs shrink to 0.13-micron SoC process

MoSys' 1T-SRAM-R technology incorporating transparent error correction has been silicon proven on UMC's 0.13-micron logic process.

MoSys' 1T-SRAM-R technology incorporating transparent error correction has been silicon proven on UMC's 0.13-micron logic process.

With this milestone, MoSys' customers can now access 1T-SRAM memory technology that has been verified on three of UMC's standard logic processes: 0.18, 0.15 and 0.13 micron.

"Given UMC's position as one of the world's top foundries, we are very pleased that our technology is now silicon-proven in their latest generation standard logic process", stated Mark-Eric Jones, Vice President and General Manager of Intellectual Property at MoSys.

"This announcement demonstrates the strong relationship between UMC and MoSys.

1T-SRAM-R technology delivers our mutual customers the highest density memory solution in a 0.13-micron standard logic process with the advantages of increased yield and reliability combined with dramatically reduced soft error rate and elimination of laser repair".

Dr CT Lee, Vice President at UMC said, "MoSys continues to provide 1T-SRAM macros that meet the memory requirements of a diverse audience.

With this latest accomplishment, designers producing 0.13-micron SoC designs can incorporate 1T-SRAM-R technology, with the confidence that MoSys' intellectual property (IP) has been proven in silicon.

Having optimal memory solutions is important as memory will take up to half of the die area in many upcoming SoC designs".

The 1T-SRAM-R technology for 0.13-micron silicon is currently available from MoSys, and is slated to be listed in UMC's IP Master online design resource and support centre in mid-February.

UMC will also offer customer specific 1T-SRAM macros, based on customer requirements, directly to customers in Q2 2003.

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