Product category:
Memory Devices and Modules
News Release from: MoSys | Subject: 1T-SRAM-Q technology
Edited by the Electronicstalk Editorial
Team on 24 July 2003
Quad-density memory shrinks to nanometre
processes
MoSys is to port its innovative quad-density 1T-SRAM-Q technology to UMC's 130 and 90nm logic processes.
MoSys is to port its innovative quad-density 1T-SRAM-Q technology to UMC's 130 and 90nm logic processes This extends the existing co-operation between the companies to offer additional optimised high-density memory solutions to UMC's foundry customers, which already include the 130nm silicon proven 1T-SRAM-R
This article was originally published on Electronicstalk on 21 Aug 2001 at 8.00am (UK)
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Off-the-shelf macros put 1T-SRAM on SoC menu
MoSys has made available a family of standard 1T-SRAM memory macros using silicon-proven 0.25- and 0.18-micron cores.
"We are pleased to co-operate with UMC for the support of our 1T-SRAM-Q technology", noted Mark-Eric Jones, Vice President and General Manager of Intellectual Property at MoSys.
"This addition broadens the range of options for UMC's foundry customers requiring integration from one to hundreds of megabits of SRAM in their SoCs".
MoSys' 1T-SRAM-Q technology achieves its exceptional density by using bit cells of just 0.5um2 in the 130nm logic process and 0.28um2 in the 90nm logic process.
Using only one additional, noncritical mask on the standard logic process, 1T-SRAM-Q enables cost-effective integration of large amounts of SRAM on SoC designs without any change to the other logic IP blocks or libraries.
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