Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: Freescale Semiconductor | Subject: PowerQUICC II processors
Edited by the Electronicstalk Editorial
Team on 18 October 2002
Comms processor enters the next
generation
The new generation of PowerQUICC II processors deliver higher performance and lower power, together with feature enhancements and a new package option.
Using Motorola's HiPerMOS7 0.13-micron process technology, the new generation of PowerQUICC II processors deliver higher performance and lower power, together with feature enhancements and a new package option "Motorola coined the term 'communications processor', and it continues to dominate that market
This article was originally published on Electronicstalk on 20 Mar 2001 at 8.00am (UK)
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The very name 'PowerQUICC' stems from the integration of two processing cores to handle specific tasks - a PowerPC ISA-based core and Motorola's RISC-based CPM", stated Eric Mantion, Senior Analyst with In-Stat/MDR.
"Motorola's next generation PowerQUICC II family carries on this leading approach, providing a substantial performance increase while continuing to deliver a well-balanced solution to handle both low level communications and higher level tasks in one integrated device".
Motorola's PowerQUICC II processors include both a high-performance embedded PowerPC ISA-based G2 core and a powerful RISC-based communications processor module (CPM).
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The CPM offloads peripheral tasks from the embedded core while providing support for multiple communication protocols - including 10/100Mbit/s Ethernet, 155Mbit/s ATM, and multichannel HDLC.
The next-generation PowerQUICC II processor retains software compatibility with the current PowerQUICC II offerings, while increasing performance by 50%.
Taking advantage of the 0.13-micron process, these devices offer significant performance increases and power savings over the current generation PowerQUICC II devices - with speeds of up to 450MHz on the core and up to 300MHz on the CPM at less than 2W.
These next-generation PowerQUICC II devices continue to enhance the PowerQUICC II architecture's industry-leading ATM support, providing up to two Utopia ports with support for up to 62 physical layer connects (PHYs) - ideal for high-density DSLAM line cards.
In addition, the new devices deliver support for USB 1.1 for high-performance small-office/home-office (SOHO) and customer premise networking equipment (CPE).
"As the market leader in communications processors, Motorola remains focused on providing our customers with a portfolio that offers a broad mix of performance and integration", commented David Perkins, vice president and general manager of Motorola's Networking and Computing Systems Group.
"With these next-generation PowerQUICC II devices, together with the announcement of our PowerQUICC III family earlier this year, we continue to expand the performance envelope of our communications processors - not only by developing new processor generations, but with continued commitment to our widely adopted PowerQUICC I and PowerQUICC II architectures".
In addition to performance and feature enhancements, the next generation PowerQUICC II devices will be offered in two packages.
The 480 lead TBGA package provides a solution that is pin-compatible with current PowerQUICC II products.
This enables existing PowerQUICC II-based designs to upgrade with minimal design changes.
The 516 lead PBGA package has been value engineered to allow customers to continue to benefit from the PowerQUICC II architecture, but at a significantly lower cost.
Consuming less than 1W, the 516 lead PBGA offerings have virtually half the footprint area of the 480 lead TBGA offerings, allowing manufacturers of high-end CPE and SOHO equipment to save on board space, cost and power consumption.
The next generation PowerQUICC II devices continue to provide a high degree of integrated features and functionality.
They provide an optimum solution for integrated control and forwarding plane processing in communications and networking equipment-such as routers, DSLAMs, remote access concentrators, telecom switching equipment and cellular basestations.
The first of the new devices is the MPC8270.
Ideal for control plane applications not requiring ATM support, the MPC8270 includes three MII/RMII interfaces for 10/100 Ethernet and 128 channels of HDLC.
The MPC8270 is offered at CPU speeds of 266, 333 and 450MHz with the CPM operating at 166, 250 and 300MHz, respectively.
Packaged in the small footprint PBGA package, the MPC8275 includes three MII/RMII interfaces for 10/100 Ethernet, two Utopia interfaces for ATM and 128 channels of HDLC.
The 8275 is offered at a CPU speed of 266MHz with the CPM operating at 166MHz.
Packaged in the pin-compatible TBGA package, the MPC8280 includes three MII/RMII interfaces for 10/100 Ethernet, two Utopia interfaces for ATM, increases HDLC channel support from 128 to 256 and includes the powerful inverse multiplexing for ATM microcode.
The MPC8280 is offered at CPU speeds of 333 and 450MHz devices with the CPM operating at 250 and 300MHz, respectively.
On-chip memory has been increased to 64K of dual-port RAM (32K for instruction RAM and 32K for data RAM), allowing more room for downloaded microcode and buffer descriptors.
Tools and software for the PowerQUICC II family supplied by Motorola and members of Motorola's Smart Networks Alliance continue to be compatible with the next generation PowerQUICC II devices.
The next-generation PowerQUICC II devices from Motorola offer a compelling balance of performance, flexibility and price.
Sampling is planned for the first quarter of 2003.
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