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Product category: Communications ICs (Wired)
News Release from: Marvell | Subject: 88SA8050 bridge chip
Edited by the Electronicstalk Editorial Team on 02 May 2003

New generation PHY enables Serial ATA II
solution

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The 88SA8050 bridge chip is the industry's first 3Gbit/s Serial ATA II solution enabling the highest throughput SATA storage systems available.

The 88SA8050 bridge chip is the industry's first 3Gbit/s Serial ATA II solution enabling the highest throughput SATA storage systems available Included in the 88SA8050 device is Marvell's next-generation PHY transceiver architecture, which supports Serial ATA II, Serial Attached SCSI and Fibre Channel, and is being used across Marvell's hard disk drive (HDD) system-on-chip (SoC), storage networking and custom ASIC solutions

With the introduction of its Serial ATA II technology, Marvell is enabling a 200% increase in throughput compared with existing Serial ATA storage systems and computing platforms.

This new product and technology introduction further strengthens Marvell's leadership position in storage electronics, and specifically, in the market for Serial ATA and other serial storage interfaces.

Serial ATA I is now in full production, having picked up considerable momentum in not only mainstream PC applications, but also in enterprise applications traditionally dominated by the more costly SCSI and Fibre Channel interfaces.

Serial ATA II is fully backward compatible with Serial ATA I, while offering a twofold increase in transfer rate, from 1.5 to 3.0Gbit/s.

In addition, this new interface generation offers a number of superset feature enhancements to the Serial ATA I standard, including native command queuing and support for Serial ATA port multiplier and port selector technology.

These enhancements will further solidify Serial ATA as the interface standard of choice for a wide variety of applications, such as servers, networked storage, desktop PCs as well as mobile and consumer electronic computing applications.

"IDC estimates that Serial ATA will become the dominant disk drive interface technology in the next few years", stated Dave Reinsel, IDC Disk Drive Research Manager.

"Worldwide shipments of Serial ATA drives are expected to exceed 70% of overall hard drive shipments in 2006.

Marvell's aggressive march to Serial ATA II technology at 3Gbit/s exemplifies the company's intent to capitalise on Serial ATA's explosive growth and tremendous volume".

With the introduction of the first commercially available 3.0Gbit/s Serial ATA product, Marvell has repeated its first-to-market achievement scored in 2001, when the company introduced the first 1.5Gbit/s Serial ATA I device, and then led the industry adoption of the interface.

"With both host and drive-side design wins for Serial ATA now in production, Marvell is focused on providing our customers with a clear forward migration path to Serial ATA II", commented Dr Alan J Armstrong, Marvell's Vice President of Marketing for the Storage Business Group.

"By working with our customers from both sides of the interface, which include PC motherboard, storage array and HDD OEMs, the resultant increased compatibility will allow Marvell to ensure the smooth migration to the latest generation Serial ATA technology".

Marvell's newest PHY architecture is a critical addition to the company's IP portfolio and is being proliferated throughout its product offerings, from HDD SoCs for leading HDD OEMs to multiple custom ASIC solutions for Serial Attached SCSI (SAS) and Fibre Channel.

This new technology is also critical to Marvell's standard product offerings for storage networking, such as its high-performance Serial ATA host controller devices.

With power consumption at less than half of the current low power Marvell Serial ATA I PHY, this advanced architecture supports not only the 1.5 and 3.0Gbit/s Serial ATA generations, but it also supports the 3.0Gbit/s SAS standard, in addition to the 1.0625, 2.125 and 4.25Gbit/s versions of the Fibre Channel interface.

Similar to all Marvell PHY technology, this new architecture features fully programmable pre-emphasis and amplitude settings for driving extended cable and backplane lengths, and boasts the industry's best jitter performance.

As with Marvell Serial ATA I PHY, this new design also implements both transmit and receive spread spectrum clocking (SSC) for reduced EMI emissions.

Additionally, the PHY offers fully automatic speed negotiation for environments with mixed generation transfer rates.

Marvell is currently sampling the 88SA8050 Serial ATA bridge chip to select customers.

The device is available in a 64-pin TQFP package.

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