Product category:
IC and Hybrid Processing Equipment
News Release from: Mears Technologies | Subject: MST for CMOS
Edited by the Electronicstalk Editorial
Team on 21 March 2008
Silicon engineering to upgrade DRAM
production
MST for CMOS will improve overall chip performance and reduce static power without introducing any new materials into existing manufacturing process flows.
Mears Technologies has signed a commercial agreement with Elpida Memory, Japan's leading global supplier of dynamic random access memory (DRAM) The two companies will work together using Mears Silicon Technology (MST for CMOS) to create more efficient chip performance
This article was originally published on Electronicstalk on 5 Mar 2004 at 8.00am (UK)
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Elpida is renowned for creating one of the world's most efficient memory ICs for computing, communications and consumer electronics applications.
By enhancing the physical properties of silicon through a breakthrough in materials engineering, Mears has demonstrated that Mears Technologies' MST for CMOS will improve overall chip performance and reduce static power without introducing any new materials into existing manufacturing process flows.
"Partnering with Mears gives us access to a company deeply experienced in materials technology for device scaling", says Elpida's Chief Technology Officer, Takao Adachi.
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"This will help boost Elpida's memory products to a much higher technology level, especially in terms of power consumption".
"We are delighted to be working with one of the world's premier memory companies", said Mears Technologies' Founder and President, Dr Robert Mears.
"We are confident that our technology will help Elpida to increase market share with differentiated products - without the need for sweeping changes in materials or huge investments in new equipment and facilities".
Using a breakthrough silicon engineering technique, Mears Technologies has developed its patented MST for CMOS technology to provide a simultaneous increase in transistor performance with dramatically reduced static power, providing a significant advantage for all applications that benefit from reduced power consumption or the need to optimise performance per watt.
The technology is designed to be fully compatible with semiconductor manufacturers' baseline processes, whether bulk CMOS, strained silicon, silicon-on-insulator or high-k/metal gate.
The improvements are achieved through a (sub) band engineering approach that is based on a deep understanding of the quantum mechanics of modern deep-submicron devices.
In its first implementation, MST for CMOS is a precision nano-doped silicon layer that is integrated into a standard CMOS flow.
The channel replacement layer can be added without introducing new materials in the fabrication process.
This "silicon-on-silicon" solution adds only a few steps to the standard CMOS manufacturing flow - at virtually no additional manufacturing cost or yield impact.
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