Product category:
Design and Development Software
News Release from: Nassda Corp | Subject: HSIM, Lexsim and Critic
Edited by the Electronicstalk Editorial
Team on 28 March 2003
Verification tools gain speed and
capacity
Nassda Corp has released version 3.0 of its HSIM, Lexsim and Critic products.
Nassda Corp has released version 3.0 of its HSIM, Lexsim and Critic products Highlights of this new release include integration with digital simulation and Verilog-A language support which can enable faster and higher-capacity IC verification for system-on-chip designs that combine analogue, mixed-signal, digital and memory IP components
This article was originally published on Electronicstalk on 7 Jun 2001 at 8.00am (UK)
Related stories
First hierarchical full-chip circuit simulator
Nassda Corp has announced version 1.3 of HSIM, which it describes as the EDA industry's first hierarchical full-chip circuit simulator.
Analysis overcomes nanometre design challenge
The latest version of HSIM analyses circuit behaviour while taking into account the electrical and parasitic effects of nanometre-scale silicon for analogue, mixed-signal, memory and SoC designs.
HSIM version 3.0 supports integration with Cadence Design System's popular NC-Sim digital simulator for enhanced full-chip verification.
The integration supports both top-down and bottom-up verification flows by allowing for either the digital or circuit-level representation to be the top-level view for the design.
Verilog testbenches can also be run directly with HSIM without a separate digital simulation and translation step by verification engineers.
Further reading
Full-chip verification includes power simulation
Lexsim from Nassda Corp is a full-chip circuit-level simulator designed for post-layout verification of large integrated circuits and their associated power networks.
Tools provide Insyte into verification
Innovative Systems and Technology Corporation is using Nassda's HSIM hierarchical full-chip simulator and analysis tool for verification of SoC integration, custom memories and analogue circuits.
Tool speeds timing signoff for nanometre ICs
Critic is a novel full-chip critical timing simulator designed for rapid post-layout analysis of cell-based digital ICs, including their associated clock networks.
This allows HSIM to work more smoothly with an existing top-down digital design and verification flow.
Unlike other proprietary approaches, Nassda's cosimulation integration uses the industry standard VPI interface, which is available with all leading Verilog simulators, to leverage customers' existing investment in digital simulation.
Lexsim version 3.0 extends its post-layout analysis capabilities by accepting all industry standard parasitic formats such as Spice LPE, DSPF and SPEF for easier integration into designers' existing physical verification and extraction flows.
In addition, parasitic reduction for large global signal networks has been added for designs, such as memories, where bit-lines and word-lines connect a large number of components.
These enhancements enable a higher performance analysis of hierarchical designs using post-layout parasitic data.
"Nassda provides leading-edge technology and best-in-class circuit verification solutions for complex IC designs", stated Dr An-Chang Deng, President of Nassda.
"We believe our version 3.0 release further strengthens our leadership in nanometre circuit simulation and analysis and sets a new standard for performance.
By integrating with NC-Sim, the industry standard high-level simulator, designers can now take advantage of a mixed-level analysis which has the speed of digital simulation in combination with HSIM's accurate and high-capacity circuit-level simulation.
Lexsim, Nassda's full-chip power net IR-drop verification product, provides further improvements in both speed and accuracy for post-layout analysis.
Nassda continues to strive to enhance the capacity, performance and ease of use of our product line with each new release".
Nassda's HSIM and Lexsim now support Open Verilog International standard Verilog-A for describing components using analogue behavioural models.
Users can benefit by being able to move to higher levels of abstraction in their analogue designs, which can improve simulation speed and their productivity.
As a result of Nassda's membership in Cadence Connections Programme, HSIM version 3.0 has a new integration into the Cadence analogue design environment.
By using the Cadence Open Analog Simulation Socket (OASIS) users will enjoy rapid waveform viewing through support of Cadence's Binary PSF format.
HSIM version 3.0 offers a new algorithm that can speed simulations for large digital CMOS designs that may include small analogue blocks.
It provides competitive digital CMOS simulation performance and complements HSIM's existing high-speed analysis of analogue, mixed-signal, and memory designs.
For all its simulation products, Nassda has expanded the set of supported MOS and bipolar device models to meet the demands for higher accuracy analysis in finer nanometre geometries and at radio frequencies (RF).
For example, Nassda's tools now support BSIM4.3, U.C.
Berkeley's latest MOS device model for nanometre-scale devices, a RPI thin-film transistor (TFT) model for LCD flat-panel display simulation, a Flash memory core cell model, and customer-proprietary device models.
For bipolar transistor designs, the HICUM model can now be used.
For RF design simulation, scattering parameter (s-parameter) descriptions of RF components are now supported for time-domain analysis.
The release 3.0 versions of HSIM, Lexsim and Critic will be available in April 2003, and will run on Sun Solaris, HP-UX, Microsoft Windows NT/2000/XP, and Linux platforms.
US time-based list prices start at $85,000 for HSIM, $180,000 for Lexsim, and $65,000 for Critic.
The digital cosimulation interface is an option to HSIM version 3.0, and the US time-based list price is $32,000.
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