National puts more bandwidth on the backplane

National Semiconductor has unveiled a range of new high-speed low-voltage differential signalling (LVDS) data transmission products.

National Semiconductor has unveiled a range of new high-speed low-voltage differential signalling (LVDS) data transmission products.

The new devices are designed to meet growing demands for higher bandwidths, greater transfer rates and lower power dissipation in backplane interface design and digital system infrastructure.

A new Bus LVDS performance leader shown by National at DesignCon 2001 is the highly integrated DS92LV16, a single-chip 16:1 LVDS serialiser/deserialiser.

The 1.28Gbit/s design can be used to construct 16 bidirectional point-point links across two pairs between two DS92LV16 parts.

In addition to all the features of National's popular 10:1 LVDS serialiser/deserialisers, the DS92LV16 offers a flexible clocking scheme that allows variable input rates from 30 to 80MHz with a +/-5% clocking disparity between chips.

Testability is enhanced and troubleshooting simplified by built-in local and line loopback modes that facilitate segregation of prespecified parts of the system by the repetition of signals back to the board (local) or back to the cable or backplane (line).

Less power is dissipated at termination by a single passive termination resistor, without costly cooling or termination power supply required with PECL designs.

Demonstrating a new level of integration, the DS92LV1260 features six 1:10 LVDS deserialisers compacted into a single package.

The new IC shrinks board space allocated to the deserialising function by more than 50%, while throttling power consumption and lowering component count.

A seventh input channel, added as an alternative path to each of the deserialiser inputs, provides built-in redundancy.

The new IC's design tracks basestation distribution of digitised data from six ADC blocks corresponding to six antenna sectors to multiple baseband-processing boards.

The DS90LV110 1:10 data distributor enables designers to extend the advantages of high-speed low-power LVDS bus technology into previously uncharted areas.

By broadcasting 10 LVDS outputs from a single LVDS input, this device is especially effective in proliferating LVDS datarates in backplane designs for cellular basestations.

It can also be used for distributing a high-speed clock signal throughout large systems.

The DS90LV110 receiver will accept LVPECL input signals, or PECL levels with attenuation networks.

Packaged in a 28 lead TSSOP and with less than 400mW power dissipation, it does not have the cooling and power supply requirements of alternative methods.

The CLC001, a serial digital cable driver, receives LVDS signals and outputs PECL signals over 75ohm cables used with telecom equipment such as digital routers and distribution amplifiers for intermediate range intra- or inter-building communications.

Output voltage levels are adjustable from 800 to 1000mV peak-peak via a single external resistor.

The device is also ideal for moving high-speed data across standard 75ohm impedance cables used with professional VCRs and digital cameras.

Operating at speeds up to 622Mbit/s, the CLC001 output meets the mask outlined for SDH by ITU-T G.703 specifications for telecommunications and SMPTE 259M requirements for video applications.

Another new addition to the Bus LVDS family is the DS92LV040 four-channel Bus LVDS transceiver.

In a 44-lead LLP package this device includes two pairs of Bus LVDS drivers and receivers with separate control signals.

This feature facilitates individual clock and data pair distribution through backplanes or cable interconnects.

National developed the DS92LV040 for busing 155Mbit/s clock and data signals in telecom systems.

Back to top