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Serdes chipset aids flexible comms system design

A National Semiconductor product story
Edited by the Electronicstalk editorial team May 7, 2003

A new serdes chipset exceeds 6Gbit/s performance at a price that is four times lower than existing solutions.

Providing backplane and cable interconnect designers with increased flexibility, National Semiconductor has released a serialiser/deserialiser (serdes) chipset exceeding 6Gbit/s performance at a price that is four times lower than existing solutions.

As part of National's broad Channel Link serdes portfolio, this chipset leverages National's leadership in low voltage differential signalling (LVDS) technology, enabling designers to optimise their system designs easily and cost-effectively.

Typical system applications for this chipset include terabit core routers, multiservice access routers, optical switches, high-performance colour printers and copiers, and storage area network (SAN) fault-tolerant servers.

National Semiconductor's DS90CR485 and DS90CR486 serdes chipset supports a full 48bit parallel bus interface.

Other products on the market serialise only 32bit on the parallel bus at a much greater cost.

"The current crop of quad 1.25 and 3.125Gbit/s serdes devices has some popularity, but they're still relatively expensive and leave designers few options for serialising buses with more than 32bit", said Alan Hutton, Marketing Manager for the Wired Communications Group at National Semiconductor in Europe.

"National differentiates itself from the pack in that it offers a unique combination of flexible 48bit parallel bus, low serial datarate and low latency, easy channel alignment, low power and small footprint".

Instead of serialising 32bit of data onto four differential pairs, the DS90CR485/6 serialises as many as 48 data bits (between 66-133MHz) onto eight differential LVDS pairs.

The clock is sent over an additional ninth LVDS pair.

This requires more serial data lines, but the lower datarates per line ease differential design requirements.

In addition, the extra-wide 48bit parallel bus not only serialises 32 data bits, but also extra data, control, and address signals.

This is a boon for designers who need to extend traditional wide parallel buses across backplanes or cables.

The chipset features adjustable transmitter pre-emphasis, DC balance and receiver deskew to drive cables up to several metres.

Customer benefits from the DS90CR485/486 chipset include: significant reduction of system cost due to low serdes per-part cost; "extra-wide" 48bit parallel bus serialises databus plus control and address signals simultaneously; lower data rate on the differential pairs helps ease design requirements on the backplane and cable; inherent channel alignment reduces system logic complexity; pre-emphasis, deskew, and DC balance extend cable lengths; and separate transmit and receive chips for low cost unidirectional and nonsymmetric links.

Additionally, National's Channel Link architecture provides obvious advantages of low overhead, flexibility and ease-of-implementation.

The new chipset helps National extend its wide range of serdes solutions to optimise system designs.

The DS90CR485 serialiser and DS90CR486 deserialiser devices are shipping now.

Offered in a 100-pin TQFP package, each is priced at $12.90 in 1000-unit quantities.

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