Product category:
Communications ICs (Wired)
News Release from: National Semiconductor | Subject: DS92LV18
Edited by the Electronicstalk Editorial
Team on 26 September 2003
Serdes provides an extra couple of bits
The industry's first LVDS 18bit serialiser/deserialiser (serdes) is designed to simplify the design of communication systems and drive down engineering costs.
The industry's first LVDS 18bit serialiser/deserialiser (serdes) is designed to simplify the design of communication systems and drive down engineering costs As part of a broad serdes portfolio, this new device extends National Semiconductor's innovative leadership in low voltage differential signalling (LVDS) technology by handling a full 18bit payload
This article was originally published on Electronicstalk on 5 Jan 2001 at 8.00am (UK)
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Many networking and communication system applications are appropriate for this product, including 3G basestations, wireless local loop systems, broadband access equipment, imaging/display interfaces and high-speed industrial links.
"Our customers asked us to add two extra bits to our popular 16bit serdes for their critical control signals", said Thomas Wirschem, Marketing Manager for the PC and Networking Group at National Semiconductor, in Europe.
"Other serdes architectures can't accommodate this kind of change.
The flexibility of our LVDS serdes architecture allowed us to easily expand from 16 to 18bit.
In applications where system designers want to avoid extra data processing on one or both ends of the serdes link, National Semiconductor's new DS92LV18 provides an elegant solution".
Two extra bits can be extremely useful to system designers.
Though databuses are typically byte-oriented (eg 8 or 16bit wide), many buses also include other nondata signals such as control, parity, frame, status etc.
Transmitting this nondata information traditionally requires adding another serdes link in parallel (doubling interconnect costs) or inserting control words or packets into the serial data stream (adding complexity through buffering and multiple clock domains).
Both these methods complicate system design, increasing system cost and design time.
With National Semiconductor's DS92LV18 18bit serdes, system designers serialise their extra signals together with their data at the existing system databus clock frequency, eliminating the overhead and hassles of previous solutions.
Available today, the DS92LV18 is offered in an 80-pin plastic quad flat pack (PQFP) package.
It is priced at $9.95 each in 1000-unit quantities.
The DS92LV18 design guide and evaluation board are available for easy design-in and qualification.
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