Product category:
Memory Devices and Modules
News Release from: NEC Electronics (Europe) | Subject: SMAFTI
Edited by the Electronicstalk Editorial
Team on 07 August 2006
SiP technology solves size restrictions
Novel system-in-package technology is capable of stacking logic and gigabit-class memory in a single package to enable high-speed, high-definition image processing in mobile devices.
NEC Corporation and NEC Electronics Corporation have unveiled a new system-in-package (SiP) technology capable of stacking logic and gigabit-class memory in a single package to enable high-speed, high-definition image processing in mobile devices The new SiP technology, SMAFTI (smart connection with feed-through interposer), features a three-dimensional (3D) chip connection whose approximately 60um gap and 50um-pitch microbump between the logic and memory devices can support transmissions up to 100Gbit/s
This article was originally published on Electronicstalk on 16 May 2001 at 8.00am (UK)
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Designers who use SMAFTI technology in cellular phones and other portable equipment that have stringent size and power constraints can achieve resolutions comparable to those achieved in high-definition television.
"The strong demand for digital video television, digital video gaming and other digital video capabilities in portable consumer devices is driving the need for high-speed image processing that realises crystal-clear resolutions", said Takaaki Kuwata, General Manager, Advanced Device Development Division, NEC Electronics Corporation.
"System-on-chip (SoC) technologies present a disadvantage in terms of development cost and memory capacity, while conventional SiP products have larger package sizes due to thicker interposers, and have limitations in signal transfer speed, wire-bonding interconnections, and side-by-side chip placement".
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"The new SMAFTI technology successfully resolves these issues and enables engineers to effectively design and manufacture high-performance systems for mobile electronic devices".
NEC Electronics and NEC developed the SMAFTI technology by leveraging three key enabling technologies: a 50um-pitch microbump interconnection technology, a 15um-thick feed-through interposer (FTI) based on superconnect technology, and a multichip assembly process.
The microbump interconnection technology makes it possible to realise low power dissipation, a small form factor, and high-speed interchip communication at more than 100Gbit/s, ten times faster than conventional technologies.
The small 50um-pitch interconnection size is the result of a silicon-to-silicon attachment process that effectively reduces the size of conventional pitch bumps and enables designers to accommodate four times the number of bumps in the same area.
This process produces high-speed data transfers and is more reliable than the conventional silicon and organic substrate attachment process.
Superconnect technology is used in chip fabrication and has a copper signal trace 15um wide and a polyimide layer 7um thick - half that of a conventional substrate.
The 15um-thick FTI, which is based on superconnect technology, makes it possible to convert a chip's wiring pitch to 50um and to fan out the pitch connection of an outer ball grid array to 500um.
As a result, the routing of signals from a logic chip with a 50um pitch and memory connection points to universal substrate terminals can be simplified.
The multichip assembly process is an enhancement of existing wafer-based manufacturing processes that are typically used for SoC manufacturing.
Memory chips are first mounted onto silicon wafers using wiring based on superconnect technology.
Then the chips and wiring layer are moulded by resin and the silicon wafer is removed.
The BGA attachment process follows.
Products featuring SMAFTI technology are expected to be available during the first quarter of 2007 in a variety of lead-free package sizes.
Availability is subject to change.
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