Novel architecture brings harmony to DTV

A vector signal processor can form the basis for a software programmable decoder for all digital TV standards.

DTV is not covered by a unique worldwide standard, because in Europe for example, the digital video broadcasting (DVB) standard exists in three variants: DVB-T (terrestrial), DVB-C (cable) and DVB-S (satellite).

DVB-H (handheld) is based on DVB-T, where the resolution of the picture is reduced.

For DVB-S, phase shift keying (PSK) has been chosen as modulation format because of the characteristics of a satellite communication.

For terrestrial as well as for cable, OFDM has been standardised as the carrier of the video stream.

The ATSC (Advanced Television Systems Committee) defined a different modulation format for the US market.

This can be an eight-level or 16-level vestigial side-band (VSB) modulation.

The Japanese market applies the ARIB system with its own standard.

For worldwide distribution of video receivers, the implementation must distinguish between the regions by using different chipsets according to the standards.

Manufacturers have the problem that international products must be designed in different variants for all regions.

The second task in designing a multistandard solution is that all chipsets for the the different standards must be applied, which increases the costs.

A solution for this problem would be a software programmable decoder for all standards.

The key issue of an programmable solution is the requirement for high computational power and the complementary type of algorithms.

Furthermore, the dissipated power should be low enough to avoid having to use a noisy fan for cooling.

The vectorial approach of a processor architecture is well suited for these tasks.

The parallel execution of operations offers high processing speed even at low clock rates, and low clock rates lead to a low power design.

A detailed look into the signal processing algorithms of DVB (Europe) and ATSC (USA) reveals that both demodulating algorithms benefit from parallel processing.

Similar thought can be applied to the video decoding and demultiplexing layer.

Currently, MPEG-2 is recommended for digital TV, although slightly differences for US and European regions are applied.

Future standards may include MPEG-4/H.264 or Microsoft's video codecs VC-1.

Both codecs are already included in the Blu-ray disc.

A parallel processor architecture like the vector signal processor (VSP) enables flexible and reprogrammable design for current and future standards.

The VSP has an architecture with a configurable number of slices and memory size resulting in scalable processing power.

It is a fixed point architecture, programmed using a VLIW word.

The VLIW word consists of slice commands, for programming the slices and a global command, for programming global arithmetic unit, I/O unit and the program sequencer.

Each slice command itself is a VLIW command consisting of micro codes allowing several slice operations in parallel.

Flexible programmability uses the maximum workload of all slices and supports vector processing of algorithms using all slices in parallel as well as sequential processing within all single slices independently.

Slice results are processed in a global arithmetic unit, eg to create a vector sum or for finding the minimum value out of the supported data vector.

The VSP allows programming of the slices through individual slice commands, enabling MIMD operations or parallel programming of all slices through one single slice command (SIMD) making the program code more compact.

An internal bus architecture enables point to point data transfer between slices without cycle delays.

All slices are synchronously controlled by a single program sequencer, which parses the VLIW program word to the slices and the global processing units, and is responsible for program flow control e.g nested loops or interrupts but also for test and debug mode.

The VSP works as stand-alone processor interfacing to an external host processor via a buffered I/O unit.

Data can be accessed via the I/O unit and using an DMA interface.

The presented architecture is ideally suited for any kind of video compression implementations.

It serves as a design platform, whereas due to its configurable and scalable architecture an optimised design can be supported.

The presented architecture can be configured to deliver the exact processing power needs, required for a dedicated implementation saving chip area size and minimising power dissipation.

It is therefore a suitable solution for all kinds of video compression applications, which differ considerably in their processing power requirements.

The key feature is the scalability, which is largely due to the parallel architecture of the VSP.

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