Product category:
Design and Development Software
News Release from: OneSpin Solutions | Subject: 360 Module Verifier
Edited by the Electronicstalk Editorial
Team on 04 June 2008
Verification promises gap-free
performance
360 MV and its GapFreeVerification process are now claimed to be the most comprehensive formal SVA verification solution on the market.
OneSpin Solutions has developed the industry's first verification solution that features gap-free RTL verification using SystemVerilog Assertions (SVA) This represents a major technical breakthrough in verification technology employing standard verification languages
This article was originally published on Electronicstalk on 23 Jan 2008 at 8.00am (UK)
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OneSpin's 360 MV ensures that all functional errors in complex digital modules and intellectual property (IP) are detected.
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Tool verifies functional equivalence between the RTL code and post-synthesis FPGA netlist, and between the post-synthesis netlist and post-place-and-route FPGA netlist.
It leverages a new, ground-breaking SVA Timing Diagram Assertion Library, Tidal, that helps users easily capture timing diagrams as SVA properties.
Users of OneSpin's 360 Module Verifier (360 MV) now can employ SVA to implement the GapFreeVerification process that slashes verification effort and ensures highest possible verification quality.
OneSpin will demonstrate the new capabilities at the Design Automation Conference in Anaheim, California.
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360 MV and its GapFreeVerification process are now claimed to be the most comprehensive formal SVA verification solution on the market.
This reduces verification effort up to five times compared with advanced testbenches, and enables verification of designs with more than 100,000 lines of RTL code - making it one of the most productive and highest-capacity formal RTL verification offerings.
GapFreeVerification is the only closed-loop verification process using SVA.
It guides users in verification planning, execution, debug and formal coverage analysis.
Automatic gap detection identifies unverified RTL functionality as well as gaps and errors in the specification.
Thus, it greatly simplifies verification planning, and eliminates the need to construct coverage models and manually analyse extensive coverage data to assess and improve verification quality.
360 MV's automatic gap detection also is the first technology to enable integration of verification planning, execution and verification quality analysis into a closed-loop process - the key to higher productivity and highest quality in verification.
TIDAL supports 360 MV's intuitive operation-based verification approach.
It enables users to directly transcribe timing diagrams that specify the intended behaviour of module-level operations into corresponding SVA properties.
Users then can employ 360 MV's automatic gap-detection to systematically find and close all gaps in the SVA property set.
Tidal's constructs, modelled in standard SVA, allow users to leverage the familiar concept of timing diagrams for formal verification, speeding learning and adoption by novices and formal experts.
According to Peter Feist, President and CEO of OneSpin: "Our customers requested a verification process that features automatic gap detection for standard SystemVerilog Assertions".
"The combination of our new Tidal library and the SVA-enabled 360 MV and GapFreeVerification process, satisfies this need".
"It sets unprecedented benchmarks for productivity, applicability and capacity in SVA-based formal verification, and ensures the highest possible verification quality".
SVA-based GapFreeVerification and Tidal are included at no extra charge in the version 5.0 release of 360 MV, available at the end of June 2008.
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