Upgrade for FPGA design software

Opal Kelly has released version 1.3.0 of its free FrontPanel software and programmer's interface (API) for use with its Xilinx FPGA modules.

Opal Kelly has released version 1.3.0 of its free FrontPanel software and programmer's interface (API) for use with its Xilinx FPGA modules.

This new release adds HDL behavioural simulation capability with behavioural models of their precompiled HDL interface modules.

The FrontPanel API provides an efficient, simple, and convenient way to communicate between user software running on a PC and user hardware running within the FPGA.

This communication occurs over a high-speed USB 2.0 link.

Instantiated precompiled HDL modules within their HDL code instantly add communication pipes to the PC without having to deal with USB implementation issues.

The FrontPanel API is available as a Windows DLL and libraries in C++, Python and Java under Windows and Linux operating systems.

Sample wrapper APIs provide access under Matlab and LabView.

This new FrontPanel release adds behavioural simulation to all of the existing precompiled HDL modules enabling customers to simulate the PC-FPGA communcation link and save valuable development time.

FrontPanel is free with the purchase of any Opal Kelly FPGA module and currently ships with the XEM3001 product.

Their new XEM3010 product with a larger FPGA and onboard SDRAM is due later this month.

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