Product category:
Communications ICs (Wired)
News Release from: Opulan Technologies | Subject: IPMux
Edited by the Electronicstalk Editorial
Team on 15 February 2007
Aggregation chip supports ADSL and VDSL
in one
Second generation DSLAM and MSAN aggregation chip offers the highest level of integration with the scale of the features that are compliant to TR101.
Opulan Technologies is sampling its second generation DSLAM and MSAN aggregation chip, the IPMux This is the first of a series of ASSPs from Opulan for the wire-speed aggregation of xDSL traffic in IP-based DSLAM or multiservice access node networks, at a central office or in remote aggregation gear
This article was originally published on Electronicstalk on 15 Nov 2005 at 8.00am (UK)
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The IPMux offers the highest level of integration with the scale of the features that are compliant to TR101 for the first time in the applications.
"We have been working together with Opulan in the past two years".
"The samples passed all tests in our lab just recently, and were designed in our systems that were sent to trial fields".
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"We expect this device to offer a value that no other competing chips can match, in terms of its cutting edge features and most of all, its level of compliance to TR101 standard".
"At the time, no one else can offer the same", said Ming Xu, Director of Product Management, Broadband Access Product Lines at ZTE's Fixed Line Network Division.
Dong Liu, Marketing Director of Opulan Technologies, said: "IPMux's introduction becomes another evidence for Opulan's system architectural expertise and VLSI design capability".
"With unique market positioning, Opulan is moving fast to become a leading fabless firm that is able to deliver leading edge features at affordable cost to OEMs".
"IPMux is just one of our tasks in development pipeline starting from xDSL, one of the hottest spots in the communication industry, adding 40 million to 50 million subscriber lines each year".
The IPMux integrates many important functional modules in a single chip, including IEEE802.1q Ethernet bridge, gigabit Ethernet MAC, AAL2 SAR, a wire-speed packet engine, and a MIPS4KEc processor.
Such design enables a dual mode operation for simultaneous support of ADSL and VDSL traffic.
Its two GE ports allow its uplink interface with 1:1 protection, link aggregation or cascading with another IPMux.
The packet engine provides flow-based queuing, shaping, hierarchical scheduling and congestion management.
The embedded MIPS processor provides flexible device configuration, and further it saves board space and BOM cost to OEMs that design a remote DSLAM that is space and cost conscious in particular.
The IPMux targets two major applications: CO DSLAM and MSAN gear; and a remote aggregation box that aggregates VDSL traffic and backhaul to a FTTN uplink, either PON or optical Ethernet.
The second scenario is especially beneficial to MTU/MDU access to carriers' infrastructure, where fibre link is available.
IPMux is based on 0.13um technology, uses BGP packaging with 727 pins.
Its power consumption is less than 3W.
Samples and a complete reference design kit are available now.
Production is expected in Q2 2007.
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