Processor PMC exploits full power of Virtex-II

Zest100 is a processor PMC that releases the full performance potential of the Xilinx Virtex-II FPGA.

Zest100 is a processor PMC that releases the full performance potential of the Xilinx Virtex-II FPGA.

64bit datapaths from the FPGA to each memory bank and the PCI controller provide enormous bandwidth and easy manipulation of 64bit precision data words.

The Virtex-II with 4 to 8 million system logic gates provides vast processing power for applications such as radar, sonar, software radio, image processing, packet processing and digital signal processing.

With its 64bit datapaths Zest100 is particularly suited to high-precision arithmetic but can also equally be used for low-precision arithmetic with very high memory and I/O bandwidths.

The PCI controller has been a particular focus to remove the classic I/O bottleneck, achieving a remarkable sustained bandwidth of 500Mbyte/s.

The 64bit datapaths to multiple double-datarate (DDR) memory banks enable multiple 128bit words to be accessed in every clock cycle.

ASIC prototyping and development of intellectual property cores also benefit from this module's logic capacity and flexibility.

Charles Sweeney, Founder, commented: "This is the platform that the Virtex-II has been waiting for, it allows the Virtex-II to deliver all its enormous potential.

64bit architecture, high-current power supplies, integrated cooling and programmable clocks up to 500MHz provide the platform for any application to achieve its targets".

There are six memory banks, each with an independent 64bit datapath.

Four banks connected to the FPGA are double datarate (DDR) SRAM with 4Mbyte each.

One further bank connected to the FPGA is 32Mbyte of DDR SDRAM.

The remaining bank is 128Mbyte of SDRAM connected to the PCI controller and accessible from both the FPGA and the PCI bus.

There is also 16Mbyte of Flash.

The PCI controller has been specially selected as it not only achieves burst rates over 500Mbytes/s but sustained rates at that level as well.

Four programmable clocks generate frequencies from 400kHz to 500MHz.

Their low jitter and high resolution provide great flexibility.

They can be used on their own or with the Virtex-II on-chip digital clock managers to enable applications to be run at their optimum frequency and with different clock domains.

The processor PMC format provides extended height that caters for three 10A power supplies, one of which is dedicated to the core logic of the FPGA.

Cooling is integrated within the module and is provided onboard by a fan cooler or heatsink, again using height allowed by the processor PMC format.

The card can plug into any PMC carrier card (for VME, cPCI, and PCI) and can form part of a complete system with other third party PMC modules.

I/O through the front panel is provided by a daughtercard that plugs onto the Zest100.

A variety of standard I/O functions is offered as well as a custom design service.

Additional digital I/O is available via a header and the PMC I/O connector.

Full software support for Windows and VxWorks operating systems is provided, together with example logic cores for all the FPGA interfaces.

These all help users get their applications up and running as quickly as possible.

Prices start at GBP 5950 or US $8950 for the 4 million gate version.

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