Core opens up interfacing options

The BK-3710S parallel ATA/IDE/ATAPI IP core uses patent-pending SpeedSelect ATA technology that allows the core to be reprogrammed to support different PIO, Multi-Word DMA and Ultra ATA timing modes.

The BK-3710S parallel ATA/IDE/ATAPI IP core contains Palmchip's patent-pending SpeedSelect ATA technology that allows the core to be reprogrammed to support different PIO, Multi-Word DMA and Ultra ATA timing modes while running at the user's selected clock frequency.

"Despite the buzz surrounding serial ATA, analysts and customers agree that the technology for today and for some time to come is parallel ATA", said Jim Venable, Senior Vice President of Palmchip.

"Our SpeedSelect parallel ATA IP core brings new flexibility, and cost savings to storage and system engineers.

They no longer have to do extensive evaluations of which parallel ATA core to license for their particular application.

One core fits all.

This is especially critical in 130 or 90nm, and beyond, due to the steady rise of tooling costs".

The SpeedSelect parallel ATA IP core from Palmchip can be reprogrammed, post silicon and in-system.

The customer need only design in the core once and then use it across many product implementations.

For example, the same system design could be used for a DVD implementation running at 66MHz or a high-performance Ultra DMA 133MHz storage device.

Palmchip's SpeedSelect parallel ATA core is designed for additional flexibility by allowing the engineer to interface the host processor through either the CoreFrame PalmBus or the Amba AHB slave interface and to connect the system memory through either the CoreFrame MBus interface or the Amba AHB master interface.

Additionally, it can be connected to most peripheral expansion buses.

The BK-3710S can be licensed either stand-alone or pre-integrated as part of the DP-1800 PalmPak and the DP-2000 AcurX SoC platform as a library component (P/N LC-3710S).

The BK-3710S SpeedSelect parallel ATA product is available today.

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