Patent application for FPGA IP Core Middleware

A breakthrough in Standards-based inter-operability and portability for embedded systems software - without sacrificing any of the performance advantages of FPGA acceleration

PrismTech, a leading provider of productivity tools and middleware, has submitted a US Patent Application for its Field Programmable Gate Array (FPGA) Integrated Circuit ORB (ICO) middleware technology.

The full Utility Patent Application follows on from the Provisional Patent Application submitted in 2005.

This breakthrough technology allows Standards-based application components to be deployed on FPGAs without the use of resource-sapping proxies, softcore GPPs or other hardware abstraction layers.

This provides a huge gain in performance and efficiency - without sacrificing any Standards-compliance or platform independence.

ICO is essentially a standards-based protocol machine implemented in hardware at the FPGA 'gate-level' which provides the key features of a software ORB required to support application inter-operability, portability and hardware independence.

Although of general value in the building of distributed embedded systems, the patent is for functional specifications originally derived from the use of FPGAs in the deployment of software-defined radio (SDR) waveform components complying with the US DoD's Software Communication Architecture (SCA).

These include but are not limited to:.

* Generic Inter ORB Protocol (GIOP) protocol machine - a VHDL / System-C / Verilog description of a CORBAR GIOP protocol machine that can be turned into a hardware device that appears as a device driver in the operating system upon which the SCA infrastructure is implemented.

* Separated CDR encoding machine - a variable encoding machine plug-on such that the GIOP machine may perform encodings other than CDR such as for example CCDR.

* Open standard BUS interface - an open architecture for being able to seamlessly interface with a variety of physical interconnect technologies from the FPGA to the bus arbiter (e.g when using PCI or VME interconnect) or fabric controller (e.g when using implementations of the RapidIO standard).

* VHDL to IDL code generator - a set of guidelines to generate skeletons in VHDL from CORBA IDL.

Such that the GIOP machine be able to dispatch calls up to servants and radio modules developed to run in the FPGA environment.

* VHDL Component container to wrapper the FPGA for SDR - using the VHDL to IDL code generator to create a soft-core Component container (implemented in VHDL, System C or Verilog) that may be used to host SCA radio elements in an FPGA yet be addressable and callable from the SCA core framework as though it was an SCA object and not an FPGA.

"PrismTech is investing heavily in leading-edge innovative technologies," said Steve Jennis, SVP Corporate Development, PrismTech.

"As we achieve breakthroughs such as ICO, we systematically protect our new intellectual property with appropriate patents".

"ICO is particularly valuable due to the growing use of FPGAs and the consequent requirement for embedded middleware to facilitate their use in distributed systems; even if that distribution is just between general-purpose processors, digital-signal processors and FPGAs on a single board".

The ICO technology is available as a COTS product from PrismTech as part of both the OpenFusion embedded middleware and Spectra SDR product families.

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