Product category:
Electronics Manufacturing Quality Assurance
News Release from: Practical Components | Subject: K and S PB series
Edited by the Electronicstalk Editorial
Team on 15 August 2002
Test die checks out bump or assembly
methods
The PB (perimeter bump or bond) series from K and S Flipchip Division is now available from Practical Components for simulating the I/O of CMOS-like devices of various pad pitches.
The PB (perimeter bump or bond) series from K and S Flipchip Division is now available from Practical Components for simulating the I/O of CMOS-like devices of various pad pitches These are used as a die standard to evaluate flip chip applications as a function of various bump, materials or assembly methods
A limited number have been designed for wire bond evaluations.
The PB6 test chip is designed with I/O pads on 6mil (152micron) pitch located on the peripheral of the die.
The 0.2 x 0.2in PB6 die contains 112 pads giving 56 daisychain pairs.
The wafer size is 5in (125mm) with a die thickness of 600 to 650 microns.
Die sizes available are 0.200 x 0.200, 0.400 x 0.400 and 0.400 x 0.600.
Die are available with a number of options including various solder formulations and bump options.
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