Beta testers wanted for IC design rule checker

Polyteda Software is offering free access to the beta version of a new tool that allows users to perform a full set of logical operations and density checks on IC layers.

Polyteda Software has released a beta version of a new tool allows users to perform a full set of logical operations and density checks on IC layers.

PowerLPU includes XOR operation that can be used as a comparison between layers in one GDSII file or layers from two different files.

PowerLPU is based on new proprietary technology that demonstrates outstanding speed of processing.

Polyteda's own benchmarks show that PowerLPU significantly outruns Caliber DRC from Mentor Graphics - in some cases by more than 10x.

And the speed advantage is greater the larger the layout.

The bigger the chip the more time a user can save by using this new product.

The company is planning to use PowerLPU as core layout engine for a new generation DRC tool.

The technology has the potential to create the fastest DRC product for handling super-large deep-submicron microchips.

The beta version of PowerLPU is available for customers free of charge until 1st October 2007.

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