Libraries speed smart-power design

Edited by the Electronicstalk editorial team Apr 25, 2005

PolarFab has released two new digital standard cell libraries for its modular 8in (200mm) Polar35 5V BiCMOS process.

PolarFab has released two new digital standard cell libraries for its modular 8in (200mm) Polar35 5V BiCMOS process.

The addition of these new libraries helps reduce design times for power management and smart-power applications, including motor control, gate drivers, and microprocessor supervisory circuits.

The first library supports synthesis place and route (SP and R) circuit design capability that requires a "gridded" standard cell library.

The 104-cell library includes logic (Verilog) and synthesis views that allow customers to use proven SP and R flows to reduce the design time of logic circuits.

The synthesis views are compatible with industry leading EDA tools such as Synopsys and Cadence.

The SP and R library features in-place-optimisation, so many of the basic logic functions have four drive strengths (d1-d4) with the same footprint.

Designers can quickly and easily alter drive strength without changing the placed and routed design.

A Library Exchange Format (LEF) file for automated place and route tools is also included.

The second library is intended for lower gate count mixed-signal designs, where the logic is specified using schematics.

The 30-cell, standard cell library gives designers a more area-efficient alternative to the SP and R library that allows them to create lower gate count circuits using proven silicon building blocks, saving time and increasing first pass yield.

Both libraries have functional VerilogA cell views that allow designers to perform logic simulations many times faster than Spice transistor level simulations, making it easier to incorporate more digital circuitry in a mixed-signal design.

Polar35's 5 V CMOS devices are based on 0.35-micron design rules that increase gate density, reducing die size compared with typical 0.5-micron CMOS processes.

The CMOS device bundle includes diffused N+ and P+ resistors, an N+ gate poly resistor, and ESD devices.

An overview of the Polar35 process is available online on PolarFab's website.

The Polar35 CMOS process is supported with a complete set of design tools, including a process design kit (PDK), models, and a comprehensive design and layout manual, as well as PolarShuttle, PolarFab's multi-project, fast track program, to manufacture prototypes.