Product category:
Intellectual Property Cores
News Release from: Plurality | Subject: HyperCore Processor
Edited by the Electronicstalk Editorial
Team on 29 January 2007
Multicore processor combines 16 RISC
cores
The HyperCore Processor incorporates 16 x 32bit RISC cores managed by a high flow rate synchroniser/scheduler, sharing a common memory on an Altera Stratix II-180 FPGA.
Plurality has announced the availability of its HyperCore Processor, the first solution to emerge from its HyperCore Architecture Line (HAL) of multicore processors, following completion of its proof of concept The design was implemented on an Altera Stratix II-180 FPGA and incorporates 16 x 32bit RISC cores managed by a high flow rate synchroniser/scheduler, sharing a common memory
This article was originally published on Electronicstalk on 16 Jan 2006 at 8.00am (UK)
Related stories
Development platform has educational aims
The EmbestUniversity is a teaching platform focused on embedded system development.
IC packaging partnership proves a success
IC packaging leader Advanced Semiconductor Engineering has announced its commitment to Ansoft's HFSS, Q3D Extractor and AnsoftLinks simulation products for IC packaging design and model extraction.
The FPGA design comprises a 4Mbit data cache, a 2Mbit instruction cache, four 32bit multipliers and four 64bit dividers.
"The success of our proof of concept shows that Plurality's unique, patented technology is able to provide the much expected performance promised by parallel processors, while offering the programmability of a serial processor", said Moshe Serfaty, Chairman and CEO.
"We are now eager to partner with customers, in various industries, interested in employing the most advanced and programmable multicore solution".
The FPGA design is now being offered to Plurality's customers on a PCI/PCIe board, from Gidel's family of Proc Boards, as an evaluation and development kit.
The board contains several configurable addons such as video and network interfaces, external IO, and others.
Additionally, Plurality offers a cycle-accurate graphic simulator for HyperCore Processors of up to 256 cores, which represents an extremely powerful development and debugging tool.
Using Plurality's novel Task Oriented Programming model, customers will be able to easily transport their applications into a powerful multicore system using tools and a development environment they already are familiar with, and very similar to the ones used to program a serial processor.
The evaluation kit enables compiling, running and debugging the code.
Once this is achieved, the code can be seamlessly executed by any of Plurality's multicore configurations, without the need to reprogram applications as core capacity increases.
For volume production of its first version of HyperCore Processors, Plurality plans to use eASIC's Nextreme, 90nm structured ASIC family, with 64 x 32bit RISC cores running at 150MHz.
Initial delivery is scheduled for Q3 2007.
Plurality's architecture is extremely scalable and will soon allow the introduction of more powerful HyperCore Processors reaching up to 256 cores.
• Plurality: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
