Product category:
Communications ICs (Wired)
News Release from: PMC-Sierra | Subject: Xenon
Edited by the Electronicstalk Editorial
Team on 12 November 2001
Hardware interoperability accelerates
optical nets
PMC-Sierra and Altera Corp have announced the successful interoperability of PMC-Sierra's Xenon family of devices and Altera's POS-PHY Level 4-compatible Apex II devices.
PMC-Sierra and Altera Corp have announced the successful interoperability of PMC-Sierra's Xenon family of devices and Altera's POS-PHY Level 4-compatible Apex II devices The POS-PHY Level 4 interface is used for data transfer between physical layer devices, such as ATM, Packet-over-SONET (POS) and Gigabit Ethernet framers, and link layer components, such as Layer 2 and Layer 3 forwarding, traffic management and switch fabric devices
This article was originally published on Electronicstalk on 2 May 2001 at 8.00am (UK)
Related stories
Level 4 devices support 10Gbit Ethernet
PMC-Sierra has unveiled the Xenon (10Gbit Ethernet for optical networks) family of clock recovery and concatenated PHY/framer devices.
Interoperability tests aid router design
PMC-Sierra and Xilinx have performed successful hardware interoperability testing between PMC-Sierra's Xenon family of devices and Xilinx Virtex-II based POS-PHY level 4 (PL4) cores.
The seamless connectivity between PMC-Sierra's Xenon family and Altera's APEX II devices will accelerate time-to-market for next-generation 10Gbit/s and high-density Gigabit Ethernet systems, including multiservice routers and switches for optical networks.
"PMC-Sierra and Altera have worked closely to advance the optical network build out by providing compatible solutions that optimise network equipment for signal integrity and reach.
Our customers product development time will be reduced with the seamless interoperability between 10Gbit/s physical layer devices and link-layer devices, through the POS-PHY Level 4 interface", said Steve Perna, vice president and general manager of PMC-Sierra's Optical Networking Division.
Further reading
Packet content classification processor speeds IP
PMC-Sierra has announced the availability of the PM2329 ClassiPI packet content classification processor for Gigabit Ethernet and OC-48 applications.
Top density for single channel OC-3 ATM/POS-PHY
The PM5384 S/UNI-1x155 from PMC-Sierra is a single channel OC-3c SONET/SDH-PHY for ATM/POS with industry standard UTOPIA Level 2 and POS-PHY Level 2 system interfaces.
"We are very pleased to have reference boards available today demonstrating this interoperability".
"The POS-PHY Level 4 interface is fully available today as an Altera MegaCore IP function", said Justin Cowling, director of IP marketing at Altera.
"The IP, together with the True-LVDST IOs on Altera's Apex II devices that are proven all the way up to 1Gbit/s, provide a fast and low risk time-to-market advantage for our customers designing system-on-a-programmable-chip (SOPC) solutions".
POS-PHY Level 4 is an industry standard multiservice system interface supporting OC-192, 10 Gigabit Ethernet and multichannel configurations, including 2.5Gbit/s OC-48, 622Mbit/s OC-12 and Gigabit Ethernet, as required by the new generation of super routers and Layer 3 switches used in multiservice voice and data networks.
The interface is flexible, supporting high-speed Packet-over-SONET (POS) Internet traffic as well as 10 Gigabit Ethernet, Gigabit Ethernet and Asynchronous Transfer Mode (ATM) applications.
POS-PHY Level 4 originated from the Saturn Development Group, co-founded by PMC-Sierra in 1992.
It has since been standardised in the OIF as System Packet Interface Level 4 (SPI-4) Phase 2 and in the ATM Forum as Frame-Based ATM Interface Level 4 (FBATM-4).
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