Product category:
Communications ICs (Wired)
News Release from: PMC-Sierra | Subject: Xilinx hardware interoperability testing
Edited by the Electronicstalk Editorial
Team on 20 December 2001
Interoperability tests aid router design
PMC-Sierra and Xilinx have performed successful hardware interoperability testing between PMC-Sierra's Xenon family of devices and Xilinx Virtex-II based POS-PHY level 4 (PL4) cores.
PMC-Sierra and Xilinx have performed successful hardware interoperability testing between PMC-Sierra's Xenon family of devices and Xilinx Virtex-II based POS-PHY level 4 (PL4) cores A collaborative effort between the two companies, the proven interoperability of the Xenon devices and the PL 4 cores will allow system architects to focus on system level aspects of the design rather than verifying connectivity
This article was originally published on Electronicstalk on 26 Feb 2001 at 8.00am (UK)
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Packet content classification processor speeds IP
PMC-Sierra has announced the availability of the PM2329 ClassiPI packet content classification processor for Gigabit Ethernet and OC-48 applications.
Level 4 devices support 10Gbit Ethernet
PMC-Sierra has unveiled the Xenon (10Gbit Ethernet for optical networks) family of clock recovery and concatenated PHY/framer devices.
As such, the interoperability will help accelerate the development of emerging metro area network (MAN) equipment such as multiservice routers and switches with support for 10 Gigabit Ethernet, High Density Gigabit Ethernet, OC-192, 4 x OC-48 POS/ATM.
"PMC-Sierra and Xilinx have worked closely in the standards committees to define the requirements for interoperable components at 10Gbit/s rates", said Steve Perna, vice president and general manager of PMC-Sierra's Optical Networking Division.
"Xilinx has been a long-standing supporter of the POS-PHY standard and together we're providing interoperable physical and link layer devices that reduce terabit system design cycles".
Further reading
Top density for single channel OC-3 ATM/POS-PHY
The PM5384 S/UNI-1x155 from PMC-Sierra is a single channel OC-3c SONET/SDH-PHY for ATM/POS with industry standard UTOPIA Level 2 and POS-PHY Level 2 system interfaces.
High-density T1/E1 processing solution
PMC-Sierra has introduced the PM4328 TECT3, the newest member of the TEMUX product family that is optimised for channelised DS3 applications.
"As a principal member of the Optical Internetworking Forum (OIF), Xilinx has been working closely with PMC-Sierra to ensure hardware interoperability with the leading physical layer solution", said Rich Sevcik, senior vice president and general manager at Xilinx.
"The combination of Xilinx cores and XENON devices give designers of MANs the ability to map proven IP into SONET/SDH, thereby satisfying the ever increasing demands for network bandwidth".
POS-PHY Level 4 is an industry standard multiservice system interface supporting OC-192, 10 Gigabit Ethernet and multichannel configurations, including 2.5Gbit/s OC-48, 622-Mbit/s OC-12 and Gigabit Ethernet, as required by the new generation of super routers and Layer 3 switches used in multiservice voice and data networks.
The interface is flexible, supporting high-speed Packet-over-SONET (POS) Internet traffic as well as 10 Gigabit Ethernet, Gigabit Ethernet and Asynchronous Transfer Mode (ATM) applications.
POS-PHY Level 4 originated from the Saturn Development Group, co-founded by PMC-Sierra in 1992.
It has since been standardized in the OIF as System Packet Interface Level 4 (SPI-4) Phase 2 and in the ATM Forum as Frame-Based ATM Interface Level 4 (FBATM-4).
The PL4 single and multichannel cores are available now for purchase as Xilinx LogicCORE products and are optimised for Virtex-II FPGAs and design tools.
Pricing for the cores are $18,000 each.
Licensing information can be found at the Xilinx IP Centre at on the company's website.
The PL4 cores are sold under the terms of the SignOnce IP License, a single set of terms for licensing FPGA-based IP cores from Xilinx and over 25 third-party providers.
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