POS-PHY cores are complementary

Modelware has released version 3.0 of its POS-PHY Level 4 (PL4)/SPI-4 Phase 2 (SPI-4.2) cores.

Modelware has released version 3.0 of its POS-PHY Level 4 (PL4)/SPI-4 Phase 2 (SPI-4.2) cores.

This version of Modelware's PluriBus PL4/SPI-4.2 Foundation and Manager cores includes advanced features such as hitless bandwidth provisioning, high-speed FIFO status channel, and a 128bit user interface option to ease the integration task for ASIC and FPGA customers.

Modelware's PluriBus PL4/SPI-4.2 cores fully comply with the Optical Internetworking Forum's (OIF) SPI-4.2 standard.

Interoperability with PMC-Sierra's Xenon family of OC-192c POS/ATM, 10 Gigabit Ethernet devices was also verified in simulation with PMC-Sierra's PL4 models.

"Interoperability with Modelware's off-the-shelf, re-usable IP cores is important for reducing our customers' product development cycles", says Steve Perna, vice president and general manager of PMC-Sierra's Optical Networking Division.

"PMC-Sierra and Modelware's success in achieving PL4/SPI-4.2 interoperability further demonstrates our commitment in providing world class support to our customers".

About Modelware's PL4/SPI-4.2 Foundation and Manager Cores Modelware's PluriBus PL4/SPI-4.2 Foundation core fully implements the PL4/SPI-4.2 protocol and provides an easy-to-use interface to the user's logic.

In addition to the functions provided by the Foundation core, the Manager core implements per-channel buffering, flow control, and credit- based data transfer scheduling.

Both cores are delivered in a ready-to-use package including a comprehensive test environment, synthesis scripts, and device layout guidelines.

Modelware has been licensing PL4/SPI-4.2 cores since November 2000 and has continued to enhance the performance and features of these products.

Among Modelware's first licensees were Azanda Network Devices and Xelerated Packet Devices.

"Modelware's support was outstanding when we were integrating the SPI-4.2 core", says Kaushik Patel, vice president of Engineering at Azanda Network Devices.

"When our first silicon devices arrived, the Modelware SPI-4.2 core was fully functional and allowed Azanda's full duplex OC-48 Traffic Manager and ATM SAR Scimitar device (AZ61100) to interoperate flawlessly with PMC-Sierra's PM5390 S/UNI-9953 device".

Joachim Roos, vice president of Engineering of Xelerated said, "Incorporating third-party IP in the high-speed SPI-4.2 10Gbit/s interfaces of our network processor has been a delicate balance of saving in-house design resources and meeting high quality demands.

We are very happy to have found that combination with the Modelware SPI-4.2 interface, which is successfully incorporated in our X10 network processor line of products".

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