Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: PMC-Sierra | Subject: RM9000x2
Edited by the Electronicstalk Editorial
Team on 16 October 2002
Multiprocessor features dual 1GHz CPU
cores
PMC-Sierra is sampling its highly integrated RM9000x2 64bit MIPS-based dual processor.
PMC-Sierra is sampling its highly integrated RM9000x2 64bit MIPS-based dual processor Manufactured in an industry-leading 0.13-micron, low-k copper process, the RM9000x2 device runs the Linux operating system at 1.0GHz
This article was originally published on Electronicstalk on 24 Jan 2008 at 8.00am (UK)
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The RM9000x2 solution draws less than 10W of total device power with each processor running at 1GHz and all of the memory and I/O interfaces running at maximum frequency.
The RM9000x2 integrates multiple high-speed bus interfaces, which include HyperTransport, DDR SDRAM, SysAD and a boot bus, to enable low latency access to main memory and high bandwidth to external I/O devices.
The RM9000x2 targets high-touch, performance-driven applications such as edge routers, DSLAMs and wireless basestations.
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"Our unique architecture provides networking and communications equipment designers greater processing power by integrating multiple gigahertz CPU cores with next-generation, high-speed bus interfaces", said Tom Riordan, vice president and general manager of PMC-Sierra's MIPS Processor Division.
"The RM9000x2 CPU subsystem is optimised for highest performance, and gives designers the flexibility to develop both control and data plane applications".
"PMC-Sierra's track record in delivering high-performance MIPS-based processors has once again been demonstrated by delivering the RM9000x2 at the intended target processor speed of 1GHz", said Markus Levy, senior analyst at MicroDesign Resources and president of EEMBC.
"The RM9000x2 dual core architecture was well designed for the high performance, flexibility and low power requirements of high-end networking applications".
The RM9000x2 CPU subsystem consists of two E9000 MIPS-64 instruction set compatible cores, both running at 1GHz.
Each core has an optimised cache architecture of high performance L1 data and instruction caches, tightly coupled with 256Kbyte of joint L2 cache providing a total of 512Kbyte of coherent L2 cache.
The L1 caches are accessed in a single CPU cycle.
Access to the L2 cache is a best-in-class five CPU cycles, or 5ns at 1GHz core frequency.
The dual E9000 cores are connected to each other by a sophisticated processor switch, which enables cache transfers between the CPUs at the core frequency.
This high-performance architecture solves multiprocessing's perennial problem of slow data transfers between processors in cache coherent systems by delivering 64Gbit/s of inter-CPU bandwidth.
To accelerate the multiprocessing capabilities, a five-state cache coherency protocol is used.
The five-state MOESI protocol extends the functionality of the standard MESI protocol to permit one processor to access modified data from the other processor's cache.
Full hardware I/O coherency is supported over the HyperTransport and SysAD interfaces, enabling I/O devices coherent access to memory without software intervention.
The dual CPU cores can run as fully cache coherent symmetric multiprocessors (SMP), or completely independent with hardware enforced protection mechanisms.
The latter mechanism might be used for separate control plane/data plane processing while the former might be used for separate ingress/egress processing.
The RM9000x2 features multiple enhancements to its cache architecture that significantly increase packet-processing performance.
Direct deposit cache provides the ability to write directly into cache over both the HyperTransport and SysAD busses, eliminating costly external memory cycles.
In auto-deposit operation, the packet header is automatically written into cache, while the payload is written into main memory.
Live-deposit operation provides the ability to dynamically write entire HyperTransport packets into cache.
Live-deposit operation also supports writing directly into cache using direct memory access (DMA).
Additional RM9000x2 cache features include fast packet cache, which allows bypassing of L2 cache on a per-page basis and further increases packet-processing performance.
The integrated high-speed bus interfaces include HyperTransport, DDR SDRAM, SysAD, and a local bus, which provides a boot bus and connectivity to slower speed devices.
The RM9000x2 HyperTransport I/O interface is a 500MHz DDR bus that delivers 16Gbit/s of raw bus bandwidth for maximum performance and provides connectivity to a wide range of high-speed networking peripherals.
The 200MHz DDR memory controller offers 25.6Gbit/s of memory bandwidth.
Up to 4Gbyte of error correcting code (ECC) protected main memory can be addressed.
The SysAD bus enables connectivity to all SysAD-based peripheral devices and delivers a seamless upgrade path for existing RM7000 family designs.
(This was Electronicstalk's Top Story on 15 October 2002).
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